• 제목/요약/키워드: metal electrode

검색결과 1,303건 처리시간 0.038초

Carrier Transport of Quantum Dot LED with Low-Work Function PEIE Polymer

  • Lee, Kyu Seung;Son, Dong Ick;Son, Suyeon;Shin, Dong Heon;Bae, Sukang;Choi, Won Kook
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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    • pp.432.2-432.2
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    • 2014
  • Recently, colloidal core/shell type quantum dots lighting-emitting diodes (QDLEDs) have been extensively studied and developed for the future of optoelectronic applications. In the work, we fabricate an inverted CdSe/ZnS quantum dot (QD) based light-emitting diodes (QDLED)[1]. In order to reduce work function of indium tin oxide (ITO) electrode for inverted structure, a very thin (<10 nm) polyethylenimine ethoxylated (PEIE) is used as surface modifier[2] instead of conventional metal oxide electron injection layer. The PEIE layer substantially reduces the work function of ITO electrodes which is estimated to be 3.08 eV by ultraviolet photoemission spectroscopy (UPS). From transmission electron microscopy (TEM) study, CdSe/ZnS QDs are uniformly distributed and formed by a monolayer on PEIE layer. In this inverted QD LED, two kinds of hybrid organic materials, [poly (9,9-di-n-octyl-fluorene-alt-benzothiadiazolo)(F8BT) + poly(N,N'-bis (4-butylphenyl)-N,N'-bis(phenyl)benzidine (poly-TPD)] and [4,4'-N,N'-dicarbazole-biphenyl (CBP) + poly-TPD], were adopted as hole transport layer having high highest occupied molecular orbital (HOMO) level for improving hole transport ability. At a low-operating voltage of 8 V, the device emits orange and red spectral radiation with high brightness up to 2450 and 1420 cd/m2, and luminance efficacy of 1.4 cd/A and 0.89 cd/A, respectively, at 7 V applied bias. Also, the carrier transport mechanisms for the QD LEDs are described by using several models to fit the experimental I-V data.

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Simulated Study on the Effects of Substrate Thickness and Minority-Carrier Lifetime in Back Contact and Back Junction Si Solar Cells

  • Choe, Kwang Su
    • 한국재료학회지
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    • 제27권2호
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    • pp.107-112
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    • 2017
  • The BCBJ (Back Contact and Back Junction) or back-lit solar cell design eliminates shading loss by placing the pn junction and metal electrode contacts all on one side that faces away from the sun. However, as the electron-hole generation sites now are located very far from the pn junction, loss by minority-carrier recombination can be a significant issue. Utilizing Medici, a 2-dimensional semiconductor device simulation tool, the interdependency between the substrate thickness and the minority-carrier recombination lifetime was studied in terms of how these factors affect the solar cell power output. Qualitatively speaking, the results indicate that a very high quality substrate with a long recombination lifetime is needed to maintain the maximum power generation. The quantitative value of the recombination lifetime of minority-carriers, i.e., electrons in p-type substrates, required in the BCBJ cell is about one order of magnitude longer than that in the front-lit cell, i.e., $5{\times}10^{-4}sec$ vs. $5{\times}10^{-5}sec$. Regardless of substrate thickness up to $150{\mu}m$, the power output in the BCBJ cell stays at nearly the maximum value of about $1.8{\times}10^{-2}W{\cdot}cm^{-2}$, or $18mW{\cdot}cm^{-2}$, as long as the recombination lifetime is $5{\times}10^{-4}s$ or longer. The output power, however, declines steeply to as low as $10mW{\cdot}cm^{-2}$ when the recombination lifetime becomes significantly shorter than $5{\times}10^{-4}sec$. Substrate thinning is found to be not as effective as in the front-lit case in stemming the decline in the output power. In view of these results, for BCBJ applications, the substrate needs to be only mono-crystalline Si of very high quality. This bars the use of poly-crystalline Si, which is gaining wider acceptance in standard front-lit solar cells.

Simulation Study of Front-Lit Versus Back-Lit Si Solar Cells

  • Choe, Kwang Su
    • 한국재료학회지
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    • 제28권1호
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    • pp.38-42
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    • 2018
  • Continuous efforts are being made to improve the efficiency of Si solar cells, which is the prevailing technology at this time. As opposed to the standard front-lit solar cell design, the back-lit design suffers no shading loss because all the metal electrodes are placed on one side close to the pn junction, which is referred to as the front side, and the incoming light enters the denuded back side. In this study, a systematic comparison between the two designs was conducted by means of computer simulation. Medici, a two-dimensional semiconductor device simulation tool, was utilized for this purpose. The $0.6{\mu}m$ wavelength, the peak value for the AM-1.5 illumination, was chosen for the incident photons, and the minority-carrier recombination lifetime (${\tau}$), a key indicator of the Si substrate quality, was the main variable in the simulation on a p-type $150{\mu}m$ thick Si substrate. Qualitatively, minority-carrier recombination affected the short circuit current (Isc) but not the opencircuit voltage (Voc). The latter was most affected by series resistance associated with the electrode locations. Quantitatively, when ${\tau}{\leq}500{\mu}s$, the simulation yielded the solar cell power outputs of $20.7mW{\cdot}cm^{-2}$ and $18.6mW{\cdot}cm^{-2}$, respectively, for the front-lit and back-lit cells, a reasonable 10 % difference. However, when ${\tau}$ < $500{\mu}s$, the difference was 20 % or more, making the back-lit design less than competitive. We concluded that the back-lit design, despite its inherent benefits, is not suitable for a broad range of Si solar cells but may only be applicable in the high-end cells where float-zone (FZ) or magnetic Czochralski (MCZ) Si crystals of the highest quality are used as the substrate.

여러 분위기에서의 저온 열처리와 폴리머 기판의 표면 morphology가 비정질 $Ta_2O_5$ 박막 커패시터의 특성에 미치는 영향 (Effects of Low Temperature Annealing at Various Atmospheres and Substrate Surface Morphology on the Characteristics of the Amorphous $Ta_2O_5$ Thin Film Capacitors)

  • 조성동;백경욱
    • 한국재료학회지
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    • 제9권5호
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    • pp.509-514
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    • 1999
  • Interest in the integrated capacitors, which make it possible to reduce the size of and to obtain improved electrical performance of an electronic system, is expanding. In this study, $Ta_2$O\ulcorner thin film capacitors for MCM integrated capacitors were fabricated on a Upilex-S polymer film by DC magnetron reactive sputtering and the effects of low temperature annealing at various atmospheres and substrate surface morphology on the capacitor characteristics were discussed. The low temperature($150^{\circ}C$) annealing produced improved capacitor yield irrespective of the annealing at mosphere. But the leakage current of the $O_2$-annealed film was larger than that of any other films. This is presumably mosphere. But the leakage current of the $O_2$-annealed film was larger than that of any other films. This is presumably due to the change of the $Ta_2$O\ulcorner film surface by oxygen, which was explained by conduction mechanism study. Leakage current and breakdown field strength of the capacitors fabricated on the Upilex-S film were 7.27$\times$10\ulcornerA/$\textrm{cm}^2$ and 1.0 MV/cm respectively. These capacitor characteristics were inferior to those of the capacitors fabricated on the Si substrate but enough to be used for decoupling capacitors in multilayer package. Roughness Analysis of each layer by AFM demonstrated that the properties of the capacitors fabricated on the polymer film were affected by the surface morphology of the substrate. This substrate effect could be classified into two factors. One is the surface morphology of the polymer film and the other is the surface morphology of the metal bottom electrode determined by the deposition process. Therefore, the control of the two factors is important to obtain improved electrical of capacitors deposited on a polymer film.

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Self-sustained n-Type Memory Transistor Devices Based on Natural Cellulose Paper Fibers

  • Martins, Rodrigo;Pereira, Luis;Barquinha, Pedro;Correia, Nuno;Goncalves, Goncalo;Ferreira, Isabel;Dias, Carlos;Correia, N.;Dionisio, M.;Silva, M.;Fortunato, Elvira
    • Journal of Information Display
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    • 제10권4호
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    • pp.149-157
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    • 2009
  • Reported herein is the architecture for a nonvolatile n-type memory paper field-effect transistor. The device was built via the hybrid integration of natural cellulose fibers (pine and eucalyptus fibers embedded in resin with ionic additives), which act simultaneously as substrate and gate dielectric, using passive and active semiconductors, respectively, as well as amorphous indium zinc and gallium indium zinc oxides for the gate electrode and channel layer, respectively. This was complemented by the use of continuous patterned metal layers as source/drain electrodes.

DNS-Zr과 DNS-Hf 바이메탈 전구체를 이용한 Gate Dielectric용 ZrSiO4 및 HfSiO4 원자층 증착법에 관한 연구 (Atomic Layer Deposition of ZrSiO4 and HfSiO4 Thin Films using a newly designed DNS-Zr and DNS-Hf bimetallic precursors for high-performance logic devices)

  • 김다영;권세훈
    • 한국표면공학회:학술대회논문집
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    • 한국표면공학회 2017년도 춘계학술대회 논문집
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    • pp.138-138
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    • 2017
  • 차세대 CMOS 소자의 지속적인 고직접화를 위해서는 높은 gate capacitance와 낮은 gate leakage current를 확보를 위한, 적절한 metal gate electrode와 high-k dielectric 물질의 개발이 필수적으로 요구된다. 특히, gate dielectric으로 적용하기 위한 다양한 high-k dielectric 물질 후보군 중에서, 높은 dielectric constant와, 낮은 leakage current, 그리고 Si과의 우수한 열적 안정성을 가지는 Zr silicates 또는 Hf silicates(ZrSiO4와 HfSiO4) 물질이 높은 관심을 받고 있으며, 이를 원자층 증착법을 통해 구현하기 위한 노력들이 있어왔다. 그러나, 현재까지 보고된 원자층 증착법을 이용한 Zr silicates 및 Hf silicates 공정의 경우, 개별적인 Zr(또는 Hf)과 Si precursor를 이용하여 ZrO2(또는 HfO2)과 SiO2를 반복적으로 증착하는 방식으로 Zr silicates 또는 Hf silicates를 형성하고 있어, 전체 공정이 매우 복잡해지는 문제점 뿐 아니라, gate dielectric 내에서 Zr과 Si의 국부적인 조성 불균일성을 야기하여, 제작된 소자의 신뢰성을 떨어뜨리는 문제점을 나타내왔다. 따라서, 본 연구에서는 이러한 문제점을 개선하기 위하여, 하나의 precursor에 Zr (또는 Hf)과 Si 원소를 동시에 가지고 있는 DNS-Zr과 DNS-Hf bimetallic precursor를 이용하여 새로운 ZrSiO4와 HfSiO4 ALD 공정을 개발하고, 그 특성을 살펴보고자 하였다. H2O와 O3을 reactant로 사용한 원자층 증착법 공정을 통하여, Zr:Si 또는 Hf:Si의 화학양론적 비율이 항상 일정한 ZrSiO4와 HfSiO4 박막을 형성할 수 있었으며, 이들의 전기적 특성 평가를 진행하였으며, dielectric constant 및 leakage current 측면에서 우수한 특성을 나타냄을 확인할 수 있었다. 이러한 결과를 바탕으로, bimetallic 전구체를 이용한 ALD 공정은 차세대 고성능 논리회로의 게이트 유전물질에 응용이 가능할 것으로 판단된다.

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Superconformal gap-filling of nano trenches by metalorganic chemical vapor deposition (MOCVD) with hydrogen plasma treatment

  • Moon, H.K.;Lee, N.E.
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2010년도 제39회 하계학술대회 초록집
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    • pp.246-246
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    • 2010
  • As the trench width in the interconnect technology decreases down to nano-scale below 50 nm, superconformal gap-filling process of Cu becomes very critical for Cu interconnect. Obtaining superconfomral gap-filling of Cu in the nano-scale trench or via hole using MOCVD is essential to control nucleation and growth of Cu. Therefore, nucleation of Cu must be suppressed near the entrance surface of the trench while Cu layer nucleates and grows at the bottom of the trench. In this study, suppression of Cu nucleation was achieved by treating the Ru barrier metal surface with capacitively coupled hydrogen plasma. Effect of hydrogen plasma pretreatment on Cu nucleation was investigated during MOCVD on atomic-layer deposited (ALD)-Ru barrier surface. It was found that the nucleation and growth of Cu was affected by hydrogen plasma treatment condition. In particular, as the plasma pretreatment time and electrode power increased, Cu nucleation was inhibited. Experimental data suggests that hydrogen atoms from the plasma was implanted onto the Ru surface, which resulted in suppression of Cu nucleation owing to prevention of adsorption of Cu precursor molecules. Due to the hydrogen plasma treatment of the trench on Ru barrier surface, the suppression of Cu nucleation near the entrance of the trenches was achieved and then led to the superconformal gap filling of the nano-scale trenches. In the case for without hydrogen plasma treatments, however, over-grown Cu covered the whole entrance of nano-scale trenches. Detailed mechanism of nucleation suppression and resulting in nano-scale superconformal gap-filling of Cu will be discussed in detail.

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곡면형 비대칭 압전복합재료 작동기 LIPCA의 설계해석/제작/성능평가 (Design Analysis/Manufacturing /Performance Evaluation of Curved Unsymmetrical Piezoelectric Composite Actuator LIPCA)

  • 구남서;신석준;박훈철;윤광준
    • 대한기계학회논문집A
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    • 제25권10호
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    • pp.1514-1519
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    • 2001
  • This paper is concerned with design, manufacturing and performance test of LIPCA ( Lightweight Piezo- composite Curved Actuator) using a top carbon fiber composite layer with near -zero CTE(coefficient of thermal expansion), a middle PZT ceramic wafer and a bottom glass/epoxy layer with high CTE. The main point of this design is to replace the heavy metal layers of THUNDER by thigh tweight fiber reinforced plastic layers without losing capabilities to generate high force and large displacement. It is possible to save weight up to about 30% if we replace the metallic backing material by the light fiber composite layer. We can also have design flexibility by selecting the fiber direction and the size of prepreg layers. In addition to the lightweight advantage and design flexibility, the proposed device can be manufactured without adhesive layers when we use epoxy resin prepreg system. Glass/epoxy prepregs, a ceramic wafer with electrode surfaces, and a graphite/epoxy prepreg were simply stacked and cured at an elevated temperature (177 $^{circ}C$ after following an autoclave bagging process. It was found that the manufactured composite laminate device had a sufficient curvature after detached from a flat mold. The analysis method of the cure curvature of LIPCA using the classical lamination theory is presented. The predicted curvatures are fairly in agreement with the experimental ones. In order to investigate the merits of LIPCA, a performance test of both LIPCA and THUNDE$^{TM}$ were conducted under the same boundary conditions. From the experimental actuation tests, it was observed that the developed actuator could generate larger actuation displacement than THUNDERT$^{TM}$.

Interfacial Layer Control in DSSC

  • Lee, Wan-In
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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    • pp.75-75
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    • 2011
  • Recently, dye-sensitized solar cell (DSSC) attracts great attention as a promising alternative to conventional silicon solar cells. One of the key components for the DSSC would be the nanocrystalline TiO2 electrode, and the control of interface between TiO2 and TCO is a highly important issue in improving the photovoltaic conversion efficiency. In this work, we applied various interfacial layers, and analyzed their effect in enhancing photovoltaic properties. In overall, introduction of interfacial layers increased both the Voc and Jsc, since the back-reaction of electrons from TCO to electrolyte could be blocked. First, several metal oxides with different band gaps and positions were employed as interfacial layer. SnO2, TiO2, and ZrO2 nanoparticles in the size of 3-5 nm have been synthesized. Among them, the interfacial layer of SnO2, which has lower flat-band potential than that of TiO2, exhibited the best performance in increasing the photovoltaic efficiency of DSSC. Second, long-range ordered cubic mesoporous TiO2 films, prepared by using triblock copolymer-templated sol-gel method via evaporation-induced self-assembly (EISA) process, were utilized as an interfacial layer. Mesoporous TiO2 films seem to be one of the best interfacial layers, due to their additional effect, improving the adhesion to TCO and showing an anti-reflective effect. Third, we handled the issues related to the optimum thickness of interfacial layers. It was also found that in fabricating DSSC at low temperature, the role of interfacial layer turned out to be a lot more important. The self-assembled interfacial layer fabricated at room temperature leads to the efficient transport of photo-injected electrons from TiO2 to TCO, as well as blocking the back-reaction from TCO to I3-. As a result, fill factor (FF) was remarkably increased, as well as increase in Voc and Jsc.

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Investigation of a Pseudo Capacitor with Polyacrylonitrile based Gel Polymer Electrolyte

  • Harankahawa, Neminda;Weerasinghe, Sandaranghe;Vidanapathirana, Kamal;Perera, Kumudu
    • Journal of Electrochemical Science and Technology
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    • 제8권2호
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    • pp.107-114
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    • 2017
  • Pseudo capacitors belong to one group of super capacitors which are consisted with non carbon based electrodes. As such, conducting polymers and metal oxide materials have been employed for pseudo capacitors. Conducting polymer based pseudo capacitors have received a great attention due to their interesting features such as flexibility, low cost and ease of synthesis. Much work has been done using liquid electrolytes for those pseudo capacitors but has undergone various drawbacks. It has now been realized the use of solid polymer electrolytes as an alternative. Among them gel polymer electrolytes (GPEs) are in a key place due to their high ambient temperature conductivities as well as suitable mechanical properties. In this study, composition of a polyacrylonitrile (PAN) based GPE was optimized and it was employed as the electrolyte in a pseudo capacitor having polypyrrole (PPy) electrodes. GPE was prepared using ethylene carbonate (EC), propylene carbonate (PC), sodium thiocyanate (NaSCN) and PAN as starting materials. The maximum room temperature conductivity of the GPE was $1.92{\times}10^{-3}Scm^{-1}$ for the composition 202.5 PAN : 500 EC : 500 PC : 35 NaSCN (by weight). Performance of the pseudo capacitor was investigated using Cyclic Voltammetry technique, Electrochemical Impedance Spectroscopy (EIS) technique and Continuous Charge Discharge (GCD) test. The single electrode specific capacity (Cs) was found out to be 174.31 F/g using Cyclic Voltammetry technique at the scan rate of 10 mV/s and within the potential window -1.2 V to 1.2 V. The same value obtained using EIS was about 84 F/g. The discharge capacity ($C_d$) was 69.8 F/g. The capacity fade over 1000 cycles was rather a low value of 4%. The results proved the suitability of the pseudo capacitor for improving the performance further.