• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2012년도 추계학술발표대회
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• pp.197-199
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• 2012

최근 GPU 의 뛰어난 부동 소수점 연산 능력을 활용하여 그래픽 이외에 다양한 응용 프로그램들의 병렬화 및 성능최적화가 활발하게 이루어지고 있다. 이러한 GPU 의 성능을 극대화하기 위해서는 메모리 계층구조 및 shared memory 를 비롯한 on-chip 메모리의 사용을 최적화하는 것이 필수적이다. 본 논문에서는 이러한 shared memory 의 사용을 최적화하기 위한 기법들을 제안하고, 이를 패턴 매칭 응용 프로그램에 적용하여 효용성을 검증한다.

• 한국전산구조공학회:학술대회논문집
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• 한국전산구조공학회 1997년도 가을 학술발표회 논문집
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• pp.35-41
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• 1997

Unit cell analyses were peformed to study the engineering properties of satin weave textile composites. Two 5-harness satin weave layers with fiber tow shifts were modeled by unit cells and repeating boundary conditions were applied at the outer surface of the unit cells. Multi-field macroelements were employed to consider the microstructure details and to effectively reduce computer memory requirements. Preliminary results indicated that the engineering properties of 5-harness satin weave textile composites can vary significantly according to the manner how the adjacent fiber tows were arranged in stacking.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 2009년도 IWAIT
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• pp.258-262
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• 2009

In this paper, we propose an effective memory reduction algorithm to reduce the amount of reference frame buffer and memory bandwidth in video encoder and decoder. In general video codecs, decoded previous frames should be stored and referred to reduce temporal redundancy. Recently, reference frames are recompressed for memory efficiency and bandwidth reduction between a main processor and external memory. However, these algorithms could hurt coding efficiency. Several algorithms have been proposed to reduce the amount of reference memory with minimum quality degradation. They still suffer from quality degradation with fixed-bit allocation. In this paper, we propose an adaptive block-based min-max quantization that considers local characteristics of image. In the proposed algorithm, basic process unit is $8{\times}8$ for memory alignment and apply an adaptive quantization to each $4{\times}4$ block for minimizing quality degradation. We found that the proposed algorithm could improve approximately 37.5% in coding efficiency, compared with an existing memory reduction algorithm, at the same memory reduction rate.

• 전자공학회논문지
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• 제50권6호
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• pp.122-130
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• 2013

메모리반도체산업이 성장함에 따라 수요와 공급이 큰 폭으로 증가하고 있다. 그 중 플래시 메모리가 스마트폰, 테블릿PC, SoC(System on Chip)산업에 많이 사용되고 있다. 플래시 메모리는 NOR-형 플래시 메모리와 NAND-형 플래시 메모리로 나뉜다. NOR-형 플래시 메모리는 BIST(Built-In Self Test), BISR(Built-In Self Repair), BIRA(Built-In Redundancy Analysis) 등 많은 연구가 진행되었지만 NAND-형 플래시 메모리 BIST는 연구가 진행되지 않았다. 현재 NAND-형 플래시 메모리 패턴 테스트는 고가의 외부 테스트 장비를 사용하여 테스트를 수행하고 있다. NAND-형 플래시 메모리에서는 블록단위로 소거, 페이지 단위로 읽기, 쓰기 동작이 가능하기 때문에 자체 내장 테스트가 존재하지 않고 외부장비에 의존하고 있다. 고가의 외부 패턴 테스트 장비에 의존해서 테스트를 수행하던 NAND-형 플래시 메모리를 외부 패턴 테스트 장비 없이 패턴 테스트를 수행할 수 있도록 두 가지의 유한 상태 머신 기반 구조를 갖고 있는 BIST를 제안한다.

• 한국정보과학회논문지:소프트웨어및응용
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• 제37권10호
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• pp.760-767
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• 2010

메모리 누수 검출을 위한 많은 도구들이 존재한다. 하자만 큰 시간적, 공간적 오버헤드로 인해 규모가 큰 제품의 개발자들은 사용을 꺼리게 된다. 이에 우리는 개발자들이 자신이 개발한 모듈만을 대상으로 유닛 테스트 시에 메모리 누수를 검출할 수 있는 기법을 고안하였다. 우리는 고정 크기 순환적 메모리 할당 기법을 우리의 목적에 맞게 확장함으로써 이것을 달성하였으며 우리의 기법을 평가하기 위해서, 간단한 데이터베이스 관리 시스템을 구현하여 그 중 일부 모듈을 대상으로 테스트 하였다. 실험 결과 우리 기법은 유닛 테스트 시에 적은 시간적, 공간적 오버헤드와 거짓 검출을 가졌다.

• 고려인삼학회:학술대회논문집
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• 고려인삼학회 2002년도 학술대회지
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• pp.20-26
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• 2002

• 한국정밀공학회지
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• 제25권5호
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• pp.82-88
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• 2008

This paper proposes a novel method of 2 dimensional shape display. Shape displays allow us to feel tile actual volume of the object, unlike conventional 2D visual displays of 3D objects. The proposed method employs a wireframe structure to present 2D or 3D objects. The wireframe is composed of small units driven by shape memory alloy (SMA) actuators. The drive unit is analogous to the agonist-antagonist system of animal musculoskeletal systems, where the SMA actuators serve as agonist and antagonist muscles. The force in the SMA actuator is controlled by electrical current. The drive unit is equipped with the locking mechanism so that it can sustain the external force exerted by the user as well as the own weight of the wireframe structure. By controlling the current into the SMA actuator and locking mechanism, we can control the angle of the drive unit. A chain of drive units enables presentation of 2 dimensional objects. 3 dimensional presentations are possible by collecting the chains of drive units.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.55-58
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• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1T FeFET) memory celt scheme which can select one unit memory cell and program/read it. To solve the selection problem of 1T FeEET memory cell array, the row direction common well is electrically isolated from different adjacent row direction column. So, we can control voltage of common well line. By applying bias voltage to Gate and Well, respectively, we can implant IT FeEET memory cell scheme which no interface problem and can bit operation. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

• 반도체디스플레이기술학회지
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• 제6권2호
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• pp.5-10
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• 2007

According to the advantageous features of flash memory, its exploitation and application in mobile and ubiquitous related devices as well as voluminous storage devices is being increased rapidly. The inherent properties that are determined by configuration of flash memory unit might restrict the promising expansion in its utilization. In this paper, we study policies based on threshold values, instead of using global search, in order to satisfy our objective that is to decrease the necessary processing cost or penalty for recycling of flash memory space at the same time minimizing the potential degradation of performance. The proposed cleaning methods create partitions of candidate memory regions, to be reclaimed as free, by utilizing global or dynamic threshold values. The impact of the proposed policies is evaluated through a number of experiments, the composition of the optimal configuration featuring the methods is tested through experiments as well.

• 전기학회논문지
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• 제59권2호
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• pp.417-422
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• 2010

When memory devices are exposed to space environments, they suffer various effects such as SEU(Single Event Upset). Memory systems for space applications are generally equipped with error detection and correction(EDAC) logics against SEUs. In this paper, several error detection and correction codes - RS(10,8) code, (7,4) Hamming code and (16,8) code - are analyzed and compared with each other. Each code is implemented using VHDL and its performances(encoding/decoding speed, required memory size) are compared. Also the failure probability equation of each EDAC code is derived, and the probability value is analyzed for various occurrence rates of SEUs which the STSAT-3 possibly suffers. Finally, the EDAC algorithm for STSAT-3 is determined based on the comparison results.