• The Journal of the Convergence on Culture Technology
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• v.6 no.2
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• pp.521-527
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• 2020

Quantum-dot cellular automata (QCA) is a technology that attracts attention as a next-generation digital circuit design technology, and several digital circuits have been proposed in the QCA environment. Content-addressable memory (CAM) is a storage device that conducts a search based on information stored therein and provides fast speed in a special process such as network switching. Existing CAM cell circuits proposed in the QCA environment have a disadvantage in that a required area and energy dissipation are large. The CAM cell is composed of a memory unit that stores information and a match unit that determines whether or not the search is successful, and this study proposes an improved QCA CAM cell by designing the memory unit in a multi-layer structure. The proposed circuit uses simulation to verify the operation and compares and analyzes with the existing circuit.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.4
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• pp.35-41
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• 2008

When memory devices are exposed to a space environment. they suffer various effects such as SEU(Single Event Upset). For these reasons, memory systems for space applications are generally equipped with error detection and correction(EDAC) logics against SEUs. In this paper, the error detection and correction strategy in the Mass Memory Unit(MMU) of the STSAT-3 is discussed. The probability equation of un-recoverable SEUs in the mass memory system is derived when the whole memory is encoded and decoded by the RS(10,8) Reed-Solomon code. Also the probability value is analyzed for various occurrence rates of SEUs which the STSAT-3 possibly suffers. The analyzed results can be used to determine the period of scrubbing the whole memory, which is one of the important parameters in the design of the MMU.

• KIPS Transactions on Computer and Communication Systems
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• v.10 no.5
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• pp.123-136
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• 2021

RPC (Remote Procedure Call)-based Graphics Processing Unit (GPU) virtualization technology is one of the technologies for sharing GPUs with multiple user virtual machines. However, in a cloud environment, unlike CPU or memory, general GPUs do not provide a resource isolation technology that can limit the resource usage of virtual machines. In particular, in an RPC-based virtualization environment, since GPU tasks executed in each virtual machine are performed in the form of multi-process, the lack of resource isolation technology causes performance degradation due to resource competition. In addition, the GPU memory competition accelerates the performance degradation as the resource demand of the virtual machines increases, and the fairness decreases because it cannot guarantee equal performance between virtual machines. This paper, in the RPC-based GPU virtualization environment, analyzes the performance degradation problem caused by resource contention when the GPU memory requirement of virtual machines exceeds the available GPU memory capacity and proposes a GPU memory management technique to solve this problem. Also, experiments show that the GPU memory management technique proposed in this paper can improve the performance of GPGPU tasks.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.36 no.8
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• pp.816-823
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• 2008

This paper describes the test results of developed high speed data processing unit using Xilinx GTP(Multi-Gigabit-Transceiver) interface and DDR-2 memory. The high speed data processing unit receives input data from packet generator at 1.25Gbps and transmits stored data to the data receiving system at 700Mbps. Therefore, DDR-2 memory controller and Xilinx GTP interface are implemented by FPGA instead of CPU to process high speed data directly.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.36 no.2
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• pp.195-201
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• 2008

This paper compares the performance of Mass Memory Unit(MMU) between Science and Technology Satellite 1(STSAT-1) and STSAT-2 from developed Proto Flight Model(PFM) for Miniaturization, lightweight and low power consumption. MMU receives the payload data at 200Kbps and transmits them to XTX at 10Mbps in the STSAT-2. The performance of PFM MMU in the Functional and space environments test satisfies the requirements of STSAT-2.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.1053-1056
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• 2004

Chunghwa Picture Tubes, LTD. (CPT) has developed a Novel TFT-LCD Driving Techniquel. This new technique is developed in combination with other state-of-the-art image processing solutions such as image compression / decompression, motion detection, and noise reduction. By applying the Novel Driving Technique to the high resolution TFT-LCD, it was found that the response time can be effectively reduced with a lower overall system cost by smaller frame memory requirement, lower EMI by less memory band-width. Likewise, higher display quality can also be achieved in that the unexpected noises generated by over-drive can be eliminated. The Novel TFT-LCD Driving Technique has been successfully implemented to the 30 inch WXGA (1280${\times}$768) resolution TFT LCD commercial TV module. It was found that the quality of moving picture was better improved compared with that of the conventional fast response driving method.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.439-440
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• 2006

This research proposes a novel method of shape display to present 3-dimensional objects. Shape displays allow us to feel the actual volume of the object, unlike conventional 2D visual displays of 3D objects. The proposed method employs a wire frame structure to present 3D objects. The wire frame is composed of small units driven by shape memory alloy(SMA) actuators. The drive unit is analogous to the agonist-antagonist system of animal musculoskeletal systems, where the SMA actuators serve as agonist and antagonist muscles. The force in the SMA actuator is controlled by electrical current. The drive unit is equipped with the locking mechanism so that it can sustain the external force exerted by the user as well as the own weight of the wire frame structure. By controlling the current into the SMA actuator and locking mechanism, we call control the angle of the drive unit. A chain of drive units enables presentation of 2 dimensional objects. 3 dimensional presentations are possible by collecting the chains of drive units.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.23-30
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• 2006

This paper presents design andd verification of a circuit that improves the control-operation problems of Stored Program Optical Computer (SPOC), which is an optical computer using $LiNbO_3$ optical switching element. Since the memory of SPOC takes the Delay Line Memory (DLM) architecture and instructions that are needless of operands should go though memory access stages, SPOC memory have problems; it takes immoderate access time and unnecessary operations are executed in Arithmetic Logical Unit (ALU) because desired operations can't be selectively executed. In this paper, improvement on circuit has been achieved by removing the memory access of instructions that are needless of operands by decoding instructions before locating operand. Unnecessary operations have been reduced by sending operands to some specific operational units, not to all the operational units in ALD. We show that total execution time of a program is minimized by using the Dual Instruction Register(DIR) architecture.

• Journal of the Korea Society of Computer and Information
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• v.20 no.11
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• pp.31-38
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• 2015

Nowadays, large size flash memory drives with more than a couple of hundreds of gigabytes are common. This paper presents an efficient cache management scheme of flash translation layer, called TPC-FTL, for large size flash memory drives. Since flash drives of large size usually contain large size RAM, we can enhance the performance of page mapping cache by using more RAM for the cache. But if the size exceeds a threshold, the existing schemes are impractical for real devices, because the time for cache manipulation becomes too long. TPC-FTL manages the cache in translation page unit, not in logical page number unit used in existing schemes. Since a translation page covers a large number of logical page numbers (for example, 512 for 2KB size page), the number of cache elements can be reduced up to a practical level. A performance evaluation shows that average response time, an important performance measure, is better than existing schemes via the effect of utilizing spacial locality in addition to temporal locality.

• Electronics and Telecommunications Trends
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• v.35 no.3
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• pp.55-65
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• 2020

With the development of nonvolatile memory technology, Intel has released the Optane datacenter persistent memory module (DCPMM) that can be deployed in the dual in-line memory module. The results of research and experiments on Optane DCPMMs are significantly different from the anticipated results in previous studies through emulation. The DCPMM can be used in two different modes, namely, memory mode (similar to volatile DRAM: Dynamic Random Access Memory) and app direct mode (similar to file storage). It has buffers in 256-byte granularity; this is four times the CPU (Central Processing Unit) cache line (i.e., 64 bytes). However, these properties are not easy to use correctly, and the incorrect use of these properties may result in performance degradation. Optane has the same characteristics of DRAM and storage devices. To take advantage of the performance characteristics of this device, operating systems and applications require new approaches. However, this change in computing environments will require a significant number of researches in the future.