• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.685-691
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• 1993

This paper introduces a PC-based image data processing unit that is composed of preprocessor board and main processor board; The preprocessor contains Inmos A110 processor and efficient H/W architecture for fast mask/logic operations at the speed of video signal rate. It is controlled by the main processor which communicates with the host PC. The main processor board contains TI TMS320C31 digital signal processor, and can access the frame memory of the processor for extra S/W tasks. We test 3*3, 5*5 masks and logic operations on 386/486/DSP and compare the result with that of the proposed unit. The result shows ours are extremely faster than conventional CPU based approach, that is, over several hundred times faster than even DSP.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.12 no.7
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• pp.688-696
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• 2000

A scheme for fault detection on the subsystem level is presented. The method uses analytical redundancy and consists in generating residuals by comparing each measurement with an estimate computed from the reference models. In this study regression neural network models are used as reference models. The regression neural network is memory-based feed forward network that provides estimates of continuous variables. The simulation result demonstrated that the proposed method can effectively detect faults in an air handling unit(AHU). The results show that the regression models are accurate and reliable estimators of the highly nonlinear and complex AHU.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.240-245
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• 2006

Viterbi decoder is composed of BMU(Branch metric Unit), ACSU(Add Compare Select Unit), and SMU(Survivor path Memory Unit). For high speed viterbi decoders, ACSU is the main bottleneck due to the compare-select and feedback operation. Thus, many studies have been advanced to solve the problem. For example, M-step look ahead technique and Minimized method are typical high speed algorithms. In this paper, we designed a bit-level ACSU(K=3, R=1/2, 4bit soft decision) based on those algorithms and switched the matrix product order in the backward direction of Minimized method so as to apply Code-Optimized-Array in order to reduce the area complexity. For experimentation, we synthesized our design by using SYNOPSYS Design compiler, with TSMC 0.18 um library, and verified the timing by using CADENCE verilog-XL.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.49 no.2
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• pp.70-77
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• 2000

This paper proposes a method of solving a unit commitment problem using tabu search (TS) which is heuristic algorithm. Ts is a local search method that starts from any initial solution and attempts to determine a better solution using memory structures. In this paper, to reduce the computation time for finding the optimal solution, changing tabu list size as intensification strategy and path relinking method as diversification strategy are proposed. To show the usefulness of the proposed method, we simulated for 10 units system and 110 units system. Numerical results show improvements in the generation costs and the computation time compared with priority list, genetic algorithm(GA), and hybrid GA.

• Journal of Communications and Networks
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• v.17 no.2
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• pp.198-202
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• 2015

This paper presents a computationally efficient implementation of a Hamming code decoder on a graphics processing unit (GPU) to support real-time software-defined radio, which is a software alternative for realizing wireless communication. The Hamming code algorithm is challenging to parallelize effectively on a GPU because it works on sparsely located data items with several conditional statements, leading to non-coalesced, long latency, global memory access, and huge thread divergence. To address these issues, we propose an optimized implementation of the Hamming code on the GPU to exploit the higher parallelism inherent in the algorithm. Experimental results using a compute unified device architecture (CUDA)-enabled NVIDIA GeForce GTX 560, including 335 cores, revealed that the proposed approach achieved a 99x speedup versus the equivalent CPU-based implementation.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.135-138
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• 2013

GPGPU(General Purpose Graphics Processing Unit) 병렬처리 시스템인 CUDA(Compute Unified Device Architecture)는 컴퓨터에서의 고속 연산 처리를 위해 많이 사용되어왔다. CUDA에서 연산 처리를 하기 위해서는 CUDA의 특성을 이해해야 한다. CUDA는 CPU(Central Processing Unit)가 처리하는 Host 영역과 GPU(Graphics Processing Unit)가 처리하는 영역인 Device 영역이 존재하며, 이 두 영역간의 데이터 복사를 통해 연산 처리를 진행한다. 이런 구조적인 특성상 메인 메모리에서 GPU 메모리로 입력 데이터를 전달해야 GPU를 이용해 연산을 처리할 수 있는 구조를 가지고 있다. 하지만 이러한 처리 구조로 인해 연산 시간과 별도로 메인 메모리와 GPU 메모리간의 데이터 복사시간이 존재하며, 추가적으로 발생하는 메모리 복사 시간으로 인해 오버헤드가 발생하게 된다. 본 논문에서는 실험을 통해 메모리 복사 시간, 연산의 반복 횟수 그리고 연산의 복잡성이 전체 성능에 어떤 영향을 미치는지 논하고자 한다.

• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.293-304
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• 2011

In this paper, we proposed a new hardware architecture for motion estimation (ME) which is the most time-consuming unit among H.264 algorithms and designed to the type of intellectual property (IP). The proposed ME hardware consists of buffer, processing unit (PU) array, SAD (sum of absolute difference) selector, and motion vector (MVgenerator). PU array is composed of 16 PUs and each PU consists of 16 processing elements (PUs). The main characteristics of the proposed hardware are that current and reference frames are re-used to reduce the number of access to the external memory and that there is no clock loss during SAD operation. The implemented ME hardware occupies 3% hardware resources of StatixIII EP3SE80F1152C2 which is a FPGA of Altera Inc. and can operate at up to 446.43MHz. Therefore it can process up to 50 frames of 1080p in a second.

• Journal of the Korea Convergence Society
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• v.4 no.1
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• pp.21-26
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• 2013

Due to a lack of research regarding disruptive technologies in domestic research, the purpose of this study is to aid in the understanding of disruptive technologies through empirical analysis of cases selected in the computer data storage industry. Analysis results have shown that SSDs, which threaten the existence of HDDs, adhere to the conditions of being a disruptive technology as first presented by Christensen(1992). SSDs are not only technologically superior to HDDs but can be mass produced due to its applicability in a vast array of product categories made possible by their miniaturization, weight reduction, and safety. This diversity of applicable fields makes it possible for mass production leading to further decrease in the unit price ultimately continuing the diffusion of this technology. By presenting empirical cases to aid in the understanding of disruptive technology, it is determined that the findings of this study contribute greatly to both academia and the business world.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.4
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• pp.143-150
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• 2013

The School Curriculum amend in 2007 mandates the contents from which students can learn the principles and concepts of computer science. Computer Science is one of the most rapidly changing subjects, and the Informatics textbook should accurately explain the basic principles and concepts based on the latest technology. However, we found that the middle school textbooks in circulation lack accuracy and consistency in describing CPU. This paper attempted to discover the root-cause of the fallacy and suggest timely and appropriate explanation based on the historical and technical analysis. According to our study, it is appropriate to state that CPU is composed of datapath and control unit. The Datapath performs operations on data and holds data temporarily, and it is composed of the hardware components such as memory, register, ALU and adder. The Control unit decides the operation types of datapath elements, main memory and I/O devices. Nevertheless, considering the technological literacy of middle school students, we suggest the terms, 'arithmetic part' and 'control part' instead of datapath and control unit.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.29 no.4
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• pp.697-708
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• 2019

In this paper, we propose and implement a method to optimize Rainbow for 8 bit MCU(Microcontroller Unit). As quantum computers have been developed, the security of existing cryptography, especially the signature algorithms, has been threatened, so it is necessary to apply a signature scheme with a quantum-resistance to IoT devices. Currently, the proposed PQC(Post Quantum Cryptography) are lattice-based, hash-based, code-based, and MQ(Multivariate Quadratic)-based cryptographic algorithms and signature schemes. In particular, MQ-based signature schemes are faster than conventional signature schemes and are suitable for IoT devices Do. However, it is difficult to apply 8-bit MCU, which has a large key length and large number of computations, to the memory and performance of IoT devices. In this paper, we propose a method of storing Rainbow, which is a MQ-based signing scheme, in 8-bit MCU by dividing the key and optimizing the computation method. By reducing the memory consumption and improving the algorithm speedily, Compare performance.