• Journal of KIISE
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• v.44 no.11
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• pp.1130-1137
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• 2017

The multi-leveling technique that stores multiple bits in a single memory cell has significantly improved the density of NAND flash memory along with shrinking processes. However, because of the side effects of the multi-leveling technique, the average write performance of MLC NAND flash memory is degraded more than twice that of SLC NAND flash memory. In this paper, we introduce existing cross-layer optimization techniques proposed to improve the performance of MLC NAND flash-based storages, and propose a new integration technique that overcomes the limitations of existing techniques by exploiting their complementarity. By fully exploiting the performance asymmetry in MLC NAND flash devices at the flash translation layer, the proposed technique can handle many write requests with the performance of SLC NAND flash devices, thus significantly improving the performance of NAND flash-based storages. Experimental results show that the proposed technique improves performance 39% on average over individual techniques.

• Journal of the Korean Institute of Intelligent Systems
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• v.11 no.4
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• pp.340-346
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• 2001

This paper proposes a new design method for the GBAM: (general bidirectional associative memory) model. Based on theoretical investigations on the GBAM: model, it is shown that the design of the GBAM:-based bidirectional associative memeories can be formulated as optimization problems called GEVPs (generalized eigenvalue problems). Since the GEVPs arising in the procedure can be efficiently solved within a given tolerance by the recently developed interior point methods, the design procedure established in this paper is very useful in practice. The applicability of the proposed design procedure is demonstrated by simple design examples considered in related studies.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.268-273
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• 2014

The forming, reset and set operation of bipolar resistive random access memory (RRAM) have been predicted by using a finite element (FE) model which includes interface effects. To the best of our knowledge, our bipolar RRAM model is applicable to realistic cell structure optimization because our model is based on the FE method (FEM) unlike precedent models.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.1
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• pp.100-106
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• 2017

In this paper, we propose a parallel optimization method of Aho-Corasick (AC) algorithm and Parallel Failureless Aho-Corasick (PFAC) algorithm using Open Computing Language (OpenCL) on Field Programmable Gate Array (FPGA). The low throughput of string matching engine causes the performance degradation of network process. Recently, many researchers have studied the string matching engine using parallel computing. FPGA's vendors offer a parallel computing platform using OpenCL. In this paper, we apply the AC and PFAC algorithm on DE1-SoC board with Cyclone V FPGA, where the optimization that considers FPGA architecture is performed. Experiments are performed considering global id, local id, local memory, and loop unrolling optimizations using PFAC algorithm. The performance improvement using loop unrolling is 129 times greater than AC algorithm that not adopt loop unrolling. The performance improvements using loop unrolling are 1.1, 0.2, and 1.5 times greater than those using global id, local id, and local memory optimizations mentioned above.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.12
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• pp.1914-1919
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• 2021

With the development of advanced industries, research on image processing hardware is essential, and timing verification at the gate level is required for actual chip operation. For FPGA-based verification, DDR3 memory interface was previously applied. But recently, as the FPGA specification has improved, DDR4 memory is used. In this case, when a previously used memory interface is applied, the timing mismatch of signals may occur and thus cannot be used. This is due to the difference in performance between CPU and memory. In this paper, the problem is solved through state optimization of the existing interface system FSM. In this process, data read speed is doubled through AXI Data Width modification. For actual case analysis, ZC706 using DDR3 memory and ZCU106 using DDR4 memory among Xilinx's SoC boards are used.

• International Journal of Computer Science & Network Security
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• v.22 no.2
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• pp.131-138
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• 2022

Soft sensors are used to anticipate complicated model parameters using data from classifiers that are comparatively easy to gather. The goal of this study is to use artificial intelligence techniques to design and build soft sensors. The combination of a Long Short-Term Memory (LSTM) network and Grey Wolf Optimization (GWO) is used to create a unique soft sensor. LSTM is developed to tackle linear model with strong nonlinearity and unpredictability of manufacturing applications in the learning approach. GWO is used to accomplish input optimization technique for LSTM in order to reduce the model's inappropriate complication. The newly designed soft sensor originally brought LSTM's superior dynamic modeling with GWO's exact variable selection. The performance of our proposal is demonstrated using simulations on real-world datasets.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.5
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• pp.245-252
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• 2018

Non-volatile RAM devices have been increasingly viewed as an alternative of DRAM main memory system. However some technologies including phase-change memory (PCM) are still suffering from relatively poor write performance as well as limited endurance. In this paper, we introduce a proactive last-level cache management to efficiently hide a low write performance of non-volatile main memory systems. The proposed method significantly reduces the cache miss penalty by proactively evicting the part of cachelines when the non-volatile main memory system is in idle state. Our trace-driven simulation demonstrates 24% performance enhancement, compared with a conventional LRU cache management, on the average.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.99-102
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• 2003

Computing environments of Embedded Systems are different from those of desktop computers so that they have resource constraints such as CPU processing, memory capacity, power, and etc.. Thus, when a desktop S/W is ported into embedded systems, optimization should be seriously considered. In this paper, we investigate several S/W optimization techniques to be considered for porting H.263 encoder into a high performance DSP, TMS320C6711. Through experiments, it is found that optimization techniques employed can make a big performance improvement.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.6
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• pp.361-367
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• 2014

This paper introduces balancing energy and memory consumption for lifetime increase of wireless sensor network. In cluster-based wireless sensor network, sensor nodes adjacent of cluster heads have a tendency to deplete their own battery energy and cluster heads occupy memory space significantly. If the nodes close to region where events occur frequently consume their energy and memory fully, network might be destroyed even though most of nodes are still alive. Therefore, it needs to balance network energy and memory with consideration of event occurrence probability so that network lifetime is increased. We show a method of balancing wireless sensor network energy and memory to organize cluster groups and elect cluster heads in terms of event occurrence probability.

• Journal of the Korean Society of Industry Convergence
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• v.24 no.5
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• pp.531-536
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• 2021

As artificial intelligence technology advances, it is being applied to various application fields. Artificial intelligence is performing well in the field of image recognition and classification. Chip design specialized in this field is also actively being studied. Artificial intelligence-specific chips are designed to provide optimal performance for the applications. At the design task, memory component optimization is becoming an important issue. In this study, the optimal algorithm for the memory size exploration is presented, and the optimal memory size is becoming as a important factor in providing a proper design that meets the requirements of performance, cost, and power consumption.