• The KIPS Transactions:PartA
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• v.13A no.7 s.104
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• pp.589-598
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• 2006

In this paper, we describe the development and optimization of an embedded Biuetooth solution on an SoC platform for real-time audio streaming over a Bluetooth wireless link. The solution includes embedded Bluetooth protocol stack and profile simplemented on a virtual operating system for portability, and other optimization techniques to fully exploit the benefits of multimedia-oriented SoC. The optimization techniques implemented in this paper are memory access minimization by using on-chip scratch pad memory, codec library optimization with DSP and parallel memory access instruction set, and dynamic audio quality adjustment regarding current wireless link status. Experimental results show that the optimized solution presented in this paper can support high-qualify audio streaming without the support of external memory.

• The Journal of the Korea Contents Association
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• v.8 no.4
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• pp.48-54
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• 2008

This paper analyzes cost tradeoffs between memory usage and computation for window-based operators in data stream environments. It identifies generic operator network constructs, and sets up a cost model for the estimation of the expected memory reduction and the computation overheads when window memory relocations are applied to each operator network construct. This cost model helps to identify the utility of window memory relocations. It also helps to apply window memory relocation to improve a query execution plan to save memory usage. The proposed approach contributes to expand the scope of query processing and optimization in data stream environments. It also provides a basis to develop a cost estimation model for the query optimization using window memory relocations.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.87-95
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• 2016

Nonvolatile memory (NVM) is being considered as an alternative of traditional memory devices such as SRAM and DRAM, which suffer from various limitations due to the technology scaling of modern integrated circuits. Although NVMs have advantages including nonvolatility, low leakage current, and high density, their inferior write performance in terms of energy and endurance becomes a major challenge to the successful design of NVM-based memory systems. In order to overcome the aforementioned drawback of the NVM, extensive research is required to develop energy- and endurance-aware optimization techniques for NVM-based memory systems. However, researchers have experienced difficulty in finding a suitable simulation tool to prototype and evaluate new NVM optimization schemes because existing simulation tools do not consider the feature of NVM devices. In this article, we introduce a NVM-based cache simulator to support rapid prototyping and evaluation of NVM-based caches, as well as energy- and endurance-aware NVM cache optimization schemes. We demonstrate that the proposed NVM cache simulator can easily prototype PRAM cache and PRAM+STT-RAM hybrid cache as well as evaluate various write traffic reduction schemes and wear leveling schemes.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.3
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• pp.75-85
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• 2008

The DBMS are widely used in embedded systems. The flash memory is used as a storage device of a embedded system. The optimizer of existing database system assumes that the storage device is disk. There is overhead to overwrite on flash memory unlike disk. The block of flash memory should be erased before write. Due to this reason, query optimization model based on disk does not adequate for flash-aware database. Especially embedded system should minimize the consumption of energy, but consumes more energy because of excessive erase operations. This paper proposes new energy based cost model of embedded database and shows the comparison between disk based cost model and energy based cost model.

• Journal of the Korea Computer Industry Society
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• v.7 no.3
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• pp.145-154
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• 2006

This paper improves algorithms of Speculative Partial Redundancy Elimination(SPRE) proposed by Knoop et al. Improving SPRE algorithm performs the execution speed optimization based on the information of the execution frequency from profiling and the memory space optimization. The first purpose of presented algorithm is to reduce in space requirements and the second purpose is to de crease the execution time. Since too much weight on execution speed optimization may cause the explosion of the memory space, it is important to consider the size of memory. This fact can be a big advantage in the embedded system which concerns the required memory size more than the execution speed In this paper we implemented the min-cut algorithm, and this algorithm used the control flow graph is constructed with network and partitioned.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.5 s.311
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• pp.1-7
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• 2006

This paper presents experimental instruction-level current consumption model for low power microcontroller ATmega128. The accessibility of instruction for internal memory decides power consumption of the microcontroller as much as 17% of difference between access instruction and non-access instruction. The power consumption for the given program will be increased in the proportional to the ratio of memory access instruction and lower level memory access in the hierarchy. Throughout the current consumption model, the power consumption can be predicted and optimized in the direction of reducing the frequency memory access. Also, the various optimization methods are introduced in terms of software and hardware viewpoints.

• Journal of Korea Multimedia Society
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• v.6 no.7
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• pp.1200-1208
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• 2003

Java Card technology allows us to run Java applications on smart cards and other memory-constrained devices. Java Card technology supports high security, portability and ability of storing and managing multiple applications. However, constrained memory resources of the Java Card Platform hinder wide deployment of the Java Card applications. Therefore, in this paper we propose a bytecode optimization algorithm to use the memory of a Java Card efficiently. Our algorithm can reduce the size of the bytecode by sharing the memory of the parameters of the catch clause in the try-catch-finally sentence.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.4
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• pp.274-282
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• 2016

This paper proposes code optimization techniques to reduce energy consumption of complex multimedia applications in a hybrid memory system with volatile dynamic random access memory (DRAM) and non-volatile spin-transfer torque magnetoresistive RAM (STT-MRAM). The proposed approach analyzes read/write operations for variables in an application. Based on the profile, variables with a high read operation are allocated to STT-MRAM, and variables with a high write operation are allocated to DRAM to reduce energy consumption. In this paper, to optimize code for real-life complicated applications, we develop a profiler, a code modifier, and compiler/link scripts. The proposed techniques are applied to a Fast Forward Motion Picture Experts Group (FFmpeg) application. The experiment reduces energy consumption by up to 22%.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.1
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• pp.1-9
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• 2014

This paper proposes a low-latency Sample Adaptive Offset filter (SAO) architecture and its Single Instruction Multiple Data (SIMD) optimization scheme to achieve fast High Efficiency Video Coding (HEVC) decoding in a multi-core environment. According to the HEVC standard and its Test Model (HM), SAO operation is performed only at the picture level. Most realtime decoders, however, execute their sub-modules on a Coding Tree Unit (CTU) basis to reduce the latency and memory bandwidth. The proposed low-latency SAO architecture has the following advantages over picture-based SAO: 1) significantly less memory requirements, and 2) low-latency property enabling efficient pipelined multi-core decoding. In addition, SIMD optimization of SAO filtering can reduce the SAO filtering time significantly. The simulation results showed that the proposed low-latency SAO architecture with significantly less memory usage, produces a similar decoding time as a picture-based SAO in single-core decoding. Furthermore, the SIMD optimization scheme reduces the SAO filtering time by approximately 509% and increases the total decoding speed by approximately 7% compared to the existing look-up table approach of HM.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.5
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• pp.177-183
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• 2012

Cell-phones functions have advanced so rapidly and they are now called 'smart-phones.' Typical approach to optimization the performance of a smartphone is the increasing the speed of device and acquiring more free memory. In this paper, we propose relatively simple techniques that average users can apply to their devices to optimize the performance. For performance upgrade, we proposed an over-clocking technique usually used by computer manufacturers. For memory optimization, we proposed deleting unnecessary apps and replacing with better-functioning apps. We also performed experimentation by applying these techniques to a popular Android phone model and presented the results.