• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.05a
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• pp.317-318
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• 2010

• Journal of the Korean Institute of Intelligent Systems
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• v.12 no.4
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• pp.353-360
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• 2002

Methods for automatic tuning of PID controllers have been on of the results of the active research on control. The proposed controller also is auto-tuning of PID controller The proposed immune algorithm has an uncomplicated structure and memory-cell mechanism as the optimization algorithm which imitates the principle of humoral immune response. We use the proposed algorithm to solve optimization of PID controller parameters. Up to now, the applications of immune algorithm have been optimization problems with non-varying system parameters. Therefore the usefulness of memory-cell mechanism in immune algorithm is without. And research of memory-cell mechanism does not give us entire satisfaction. This paper proposes the immune algorithm using a memory-cell mechanism which can be the application of system with nonlinear varying parameters. To verify performance of the proposed immune algorithm, the speed control of nonlinear DC motor are performed. The results of Computer simulations represent that the proposed immune algorithm shows a fast convergence speed and a good control performances under the varying system parameters.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.233-236
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• 1998

In this paper, we present a novel approach named a shared library as an active memory object for application software development of large-scale real-time systems. Unlike the general passive shared memory, shared library proposed in this paper can be activated as an execution object. Moreover this is not tightly coupled with application programs unlike the normal libraries. To implement this mechanism, operating system makes the shared memory as an active object and shared library realizes the indirect call structure. This mechanism enhanced the utilization of main memory and communication performance. And this is successfully applied to the HANbit ACE ATM switching system and the TDX-10 switching system.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.2
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• pp.33-43
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• 1993

Lock mechanism is essential for synchronization on the multiprocessor systems. Lock mechanism needs to reduce the time for lock operation in low lock contention. Lock mechanism must consider the case of the high lock contention. The conventional lock control scheme in memory results in the increase of bus traffic and memory utilization in lock operation. This paper suggests a lock scheme which stores the lock data in cache and manages it efficiently to reduce the time spent in lock operation when the lock contention is low on a multiprocessor system built on HiPi-bus(Highly Pipelined bus). This paper also presents the design of the HIPi-CLOCK (Highly Pipelined bus Cache LOCK mechanism) which transfere the data from on cache to another when the lock contention is high. The designed simulator compares the conventional lock scheme which controls the lock in memory with the suggested HiPi-CLOCK scheme in terms of the RMW(Read-Modify-Write) operation time using simulated trace. It is shown that the suggested lock control scheme performance is over twice than that of the conventional method in low lock contention. When the lock contention is high, the performance of the suggested scheme increases as the number of the shared lock data increases.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.318-318
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• 2012

A graphene layer is most important materials in resent year to enhance the electrical properties of semiconductor device due to high mobility, flexibility, strong mechanical resistance and transparency[1,2]. The resistance switching memory with the graphene layer have been reported for next generation nonvolatile memory device[3,4]. Also, the graphene layer is able to improve the electrical properties of memory device because of the high mobility and current density. In this study, the resistance switching memory device with metal-oxide nano-particles embedded in polyimide layer on the graphene mono-layer were fabricated. At first, the graphene layer was deposited $SiO_2$/Si substrate by using chemical vapor deposition. Then, a biphenyl-tetracarboxylic dianhydride-phenylene diamine poly-amic-acid was spin coated on the deposited metal layer on the graphene mono-layer. Then the samples were cured at $400^{\circ}C$ for 1 hour in $N_2$ atmosphere after drying at $135^{\circ}C$ for 30 min through rapid thermal annealing. The deposition of aluminum layer with thickness of 200 nm was done by a thermal evaporator. The electrical properties of device were measured at room temperature using an HP4156a precision semiconductor parameter analyzer and an Agilent 81101A pulse generator. We will discuss the switching mechanism of memory device with metal-oxide nano-particles on the graphene mono-layer.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.5
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• pp.3121-3131
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• 2014

Vulnerabilities related to memory have been known as major threats to the security of a computer system. Actually, the number of attacks using memory vulnerability has been increased. Accordingly, various memory protection mechanisms have been studied and implemented on operating system while new attack techniques bypassing the protection systems have been developed. Especially, buffer overflow attacks have been developed as Return-Oriented Programing(ROP) and Jump-Oriented Programming(JOP) called Code Re-used attack to bypass the memory protection mechanism. Thus, in this paper, I analyzed code re-use attack techniques emerged recently among attacks related to memory, as well as analyzed various detection mechanisms proposed previously. Based on the results of the analyses, a mechanism that could detect various code re-use attacks on a binary level was proposed. In addition, it was verified through experiments that the proposed mechanism could detect code re-use attacks effectively.

• International Journal of Internet, Broadcasting and Communication
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• v.14 no.3
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• pp.161-170
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• 2022

Recently, NAND-type flash memory has been regarded to be new promising storage media for large-scale database systems. For flash memory to be employed for that purpose, we need to reduce its expensive update cost caused by the inablity of in-place updates. To remedy such a drawback in flash memory, we propose a new flash-aware buffering scheme that enables virtual flushing of dirty pages. To this end, we slightly alter the tradional algorithms used for the logging scheme and buffer management scheme. By using the mechanism of virtual flushing, our proposed buffering scheme can efficiently prevent the frequenct occureces of page updates in flash storage. Besides the advantage of reduced page updates, the proposed viurtual flushing mechanism works favorably for shorneing a recocery time in the presense of failure. This is because it can reduce the time for redo actions during a recovry process. Owing to those two benefits, we can say that our scheme couble be very profitable when it is incorporated into cutting-edge flash-based database systems.

• Sleep Medicine and Psychophysiology
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• v.4 no.1
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• pp.15-28
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• 1997

Longterm memory is encoded in the neuronal connectivities of the brain. The most successful models of human memory in their operations are models of distributed and self-organized associative memory, which are founded in the principle of simulaneous convergence in network formation. Memory is not perceived as the qualities inherent in physical objects or events, but as a set of relations previously established in a neural net by simultaneousy occuring experiences. When it is easy to find correlations with existing neural networks through analysis of network structures, memory is automatically encoded in cerebral cortex. However, in the emergence of informations which are complicated to classify and correlated with existing networks, and conflictual with other networks, those informations are sent to the subcortex including hippocampus. Memory is stored in the form of templates distributed across several different cortical regions. The hippocampus provides detailed maps for the conjoint binding and calling up of widely distributed informations. Knowledge about the distribution of correlated networks can transform the existing networks into new one. Then, hippocampus consolidats new formed network. Amygdala may enable the emotions to influence the information processing and memory as well as providing the visceral informations to them. Cortico-striatal-pallido-thalamo-cortical loop also play an important role in memory function with analysis of language and concept. In case of difficulty in processing in spite of parallel process of informations, frontal lobe organizes theses complicated informations of network analysis through temporal processing. With understanding of brain mechanism of memory and information processing, the brain mechanism of mental phenomena including psychopathology can be better explained in terms of neurobiology and meuropsychology.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.9 no.2
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• pp.49-60
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• 1999

IC 카드의 하드웨어적인 제약으로 대부분의 IC 카드는 대칭키 알고리즘을 사용하고 있지만 IC 카드 하드웨어 제조 기술의 발전으로 앞으로는 보안성이 우수한 비대 칭키 알고리즘이 많이 사용될 것이다. 그리고 IC 카드의 가장 큰 제약적 중 하나는 메모리 용량의 한계이다. 따라서 보안상 안전하면서도 메모리를 적게 사용하는 IC 카드 운영체제의 구현을 중요한 문제이다. 그래서 본 논문에서는 다양한 종류의 키 알고리즘을 수용할 수 있는 키 파일 탐색 기법을 제안하였다. 또한 데이터 파일 헤더에 잠금 필드를 삽입하여 보안성을 향상시켰으며 메모리 사용량을 줄일 수 있도록 데이터 파일 헤더만을 이용한 파일 탐색 기법과 자유 공간 탐색 기법을 제안하였다. Because of the evolution of IC card hardware fabrication technologies IC card will be able to accept asymmetric key encryption algorithm in the future. One of the most restrictive points of IC card is memory capacity. Therefore it is an important problem to design a secure IC card operating system using memory in small. In this paper we proposed a key file search mechanism using a key length field inserted in a key file header structure. The key file search mechanism makes IC card execute any key-based encryption algorithm. In addition we proposed inserting a lock field in data file header structure. The lock field intensifies the security of a data file. Finally we proposed a data file search mechanism and free space search mechanism using only data file header. The file system using these mechanisms spends smaller memory than that using a file description table and record of unallocated space.

• Korean Journal of Cognitive Science
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• v.17 no.3
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• pp.207-229
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• 2006

Two experiments examined the relation of working memory capacity and the inhibition mechanism in working memory. Experiment 1 demonstrated that the high WM span group inhibited irrelevant information selectively and the low WM span group maintained both relevant and irrelevant information within WM. Experiment 2 showed that there were similar patterns of response time between high and low WM span groups in the lexical decision task. These results suggest that the ability to maintain relevant information and inhibit irrelevant information selectively in WM is an important factor of individual differences in working memory.