• Journal of Oriental Neuropsychiatry
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• v.28 no.2
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• pp.123-136
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• 2017

Objectives: The objective of this study is to investigate the anti-amnesic effects of AR, Aucklandiae Radix, ground powder on scopolamine (Sco)-induced memory impairment in mice (C57BL/6) through its favorable acetylcholine (ACh) and acetylcholinesterase (AChE) activity, Choline acetyltransferase (ChAT) mRNA expression, and antioxidant effect. Methods: Six groups, a total of 20 intact or 100 Sco treated mice, were selected based on their body weights and were used in this study. Half of the mice in each group were used for the passive avoidance task test and the measurements of hippocampus ACh content, AChE activity and ChAT mRNA expression. The remaining half of the mice in each group were used for the Morris water maze test and cerebral antioxidant defense system measurement. Results: Marked decreases in step-through latency times in the passive avoidance task test and increases in escape latency times in the Morris water maze test were observed with decreases in the hippocampus ACh content and ChAT mRNA expression, and increases in the hippocampal AChE activities, as a result of Sco intraperitoneal treatment, in the present study. In addition, destruction of the cerebral cortex antioxidant defense systems was observed in Sco control mice as compared with intact vehicle control mice. However, 28 days of continuous oral pre-treatment with AR ground powder at doses of 400, 200 and 100 mg/kg markedly and dose-dependently inhibited the Sco treatment-related amnesia. Conclusions: The results prove that oral administration of AR ground powder reduces Sco-induced memory impairment. This is because it can preserve ACh, related to ChAT mRNA expression, cause AChE inhibition, and activate the cerebral antioxidant defense system.

• Biomolecules & Therapeutics
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• v.25 no.3
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• pp.249-258
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• 2017

To examine the effect of biflorin, a component of Syzygium aromaticum, on memory deficit, we introduced a scopolamine-induced cognitive deficit mouse model. A single administration of biflorin increased latency time in the passive avoidance task, ameliorated alternation behavior in the Y-maze, and increased exploration time in the Morris water maze task, indicating the improvement of cognitive behaviors against cholinergic dysfunction. The biflorin-induced reverse of latency in the scopolamine-treated group was attenuated by MK-801, an NMDA receptor antagonist. Biflorin also enhanced cognitive function in a naïve mouse model. To understand the mechanism of biflorin for memory amelioration, we performed Western blot. Biflorin increased the activation of protein kinase C-${\zeta}$ and its downstream signaling molecules in the hippocampus. These results suggest that biflorin ameliorates drug-induced memory impairment by modulation of protein kinase C-${\zeta}$ signaling in mice, implying that biflorin could function as a possible therapeutic agent for the treatment of cognitive problems.

• Journal of Oriental Neuropsychiatry
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• v.30 no.3
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• pp.221-235
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• 2019

Objectives: The purpose of this study was to confirm the anti-amnesic effects of Bunsimgieum (BSGE) through its favorable acetylcholine (ACh) and, acetylcholinesterase (AChE) activity, choline acetyltransferase (ChAT) mRNA expressions, and antioxidant effect on scopolamine (Sco)-induced memory impairment in C57BL/6 mice. Methods: Six groups, a total of 20 intact or 100 Sco-induced mice were used in this study, based on their body weight. Half of each group underwent passive avoidance tests and the measurement of hippocampus AChE activity, ACh content, and ChAT mRNA expression, The remaining half of each group underwent a Morris water-maze test and antioxidant defense system measurement as well. Results: Significant reductions in the step-through latency times from the passive avoidance test and reductions in the escape latency times from the Morris water-maze test were observed with increases of hippocampal AChE activities and, reductions in ACh contents and ChAT mRNA expression in hippocampus, as a result of Sco intraperitoneal treatment, in this study. Additionally, the increases in cerebral cortical MDA levels and, reductions in GSH contents, SOD activities, and CAT activities were demonstrated in the Sco control mice compared with the intact vehicle control mice, respectively. However, 28 days of consecutive oral pre-treatment of BSGE hot water extracts of 400, 200, and 100 mg/kg, respectively, markedly and dose-dependently inhibited Sco treatment-related amnesia. Conclusions: The results demonstrate that the oral administration of BSGE hot water extracts reduces Sco-induced memory impairment, through preserving ACh, related to ChAT mRNA expressions, causes AChE inhibition, and enhances the cerebral antioxidant defense system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.05a
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• pp.115-117
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• 2022

Whitebox encryption technique is a method of preventing exposure of encryption keys by mixing encryption key information with a software-based encryption algorithm. Whitebox encryption technique is attracting attention as a technology that replaces conventional hardware-based security encryption techniques by making it difficult to infer confidential data and keys by accessing memory with unauthorized reverse engineering analysis. However, in the encryption and decryption process, a large lookup table is used to hide computational results and encryption keys, resulting in a problem of slow encryption and increased memory size. In particular, it is difficult to apply whitebox cryptography to low-cost, low-power, and light-weight Internet of Things products due to limited memory space and battery capacity. In addition, in a network environment that requires real-time service support, the response delay time increases due to the encryption/decryption speed of the whitebox encryption, resulting in deterioration of communication efficiency. Therefore, in this paper, we analyze whether the AES-based whitebox(WBC-AES) proposed by S.Chow can satisfy the speed and memory requirements based on the experimental results.

• Journal of Oriental Neuropsychiatry
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• v.10 no.2
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• pp.115-126
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• 1999

This study was conducted to find out the effects of Woohwangchungsimwon on learning and memory in the NOS inhibitor treated rats. The Morris water maze was used in evaluating them. The result of the study was summarized as follows. 1. In the learning test, three groups have showed a gradual improvement of learning ability by repeating the trials in Morris water maze. WHCS group have showed statistical improvement than control group at 4,5,6 trial(p<0.05, p<0.01, p<0.01). 2. In the memory test, the first latency of WHCH group was statistically shortened than that of control group(p<0.05). 3. In the memory test, there was no statistical difference in the entry number between WHCH group and control. 4. In the memory test, there was no statistical difference in the memory score between WHCH group and control. The result of this experimental study presents that Woohwangchungsimwon has the improving effect on impaired learning and memory in NOS inhibitor treated rats, and implies that Woohwangchungsimwon may be one of the useful prescription for the treatment of vascular dementia after cerebral ischemia.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.262-269
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• 2005

Semiconductor scientists and engineers ideally desire the faster but the cheaper non-volatile memory devices. In practice, no single device satisfies this desire because a faster device is expensive and a cheaper is slow. Therefore, in this paper, we use heterogeneous non-volatile memories and construct an efficient hierarchy for them. First, a small RAM device (e.g., MRAM, FRAM, and PRAM) is used as a write buffer of flash memory devices. Since the buffer is faster and does not have an erase operation, write can be done quickly in the buffer, making the write latency short. Also, if a write is requested to a data stored in the buffer, the write is directly processed in the buffer, reducing one write operation to flash storages. Second, we use many types of flash memories (e.g., SLC and MLC flash memories) in order to reduce the overall storage cost. Specifically, write requests are classified into two types, hot and cold, where hot data is vulnerable to be modified in the near future. Only hot data is stored in the faster SLC flash, while the cold is kept in slower MLC flash or NOR flash. The evaluation results show that the proposed hierarchy is effective at improving the access time of flash memory storages in a cost-effective manner thanks to the locality in memory accesses.

• International journal of advanced smart convergence
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• v.8 no.1
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• pp.9-17
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• 2019

In this article, we present a performance enhancement scheme for mobile applications by adopting persistent memory. The proposed scheme supports the deadline guarantee of real-time applications like a video player, and also provides reasonable performances for non-real-time applications. To do so, we analyze the program execution path of mobile software platforms and find two sources of unpredictable time delays that make the deadline-guarantee of real-time applications difficult. The first is the irregular activation of garbage collection in flash storage and the second is the blocking and time-slice based scheduling used in mobile platforms. We resolve these two issues by adopting high performance persistent memory as the storage of real-time applications. By maintaining real-time applications and their data in persistent memory, I/O latency can become predictable because persistent memory does not need garbage collection. Also, we present a new scheduler that exclusively allocates a processor core to a real-time application. Although processor cycles can be wasted while a real-time application performs I/O, we depict that the processor utilization is not degraded significantly due to the acceleration of I/O by adopting persistent memory. Simulation experiments show that the proposed scheme improves the deadline misses of real-time applications by 90% in comparison with the legacy I/O scheme used in mobile systems.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.4
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• pp.1922-1940
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• 2019

IP address lookup is a function to determine nexthop for a given destination IP address. It takes an important role in modern routers because of its computation time and increasing Internet traffic. TCAM-based IP lookup approaches can exploit the capability of parallel searching but have a limitation of its size due to latency, power consumption, updatability, and cost. On the other hand, multibit trie-based approaches use SRAM which has relatively low power consumption and cost. They reduce the number of memory accesses required for each lookup, but it still needs several accesses. Moreover, the memory efficiency and updatability are proportional to the number of memory accesses. In this paper, we propose a novel architecture using an Indexed Multibit Trie (IMT) which is based on combined TCAM and SRAM. In the proposed architecture, each lookup takes at most two memory accesses. We present how the IMT is constructed so as to be memory-efficient and fast updatable. Experiment results with real-world forwarding tables show that our scheme achieves good memory efficiency as well as fast updatability.

• Journal of the Semiconductor & Display Technology
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• v.22 no.2
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• pp.6-10
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• 2023

High-potential data can be predicted and stored in the cache to prevent cache misses, thus reducing the processor's request and wait times. As a result, the processor can work non-stop, hiding memory latency. By utilizing the temporal/spatial locality of memory access, the prefetcher introduced to improve the performance of these computers predicts the following memory address will be accessed. We propose a prefetcher that applies the GRU model, which is advantageous for handling time series data. Display the currently accessed address in binary and use it as training data to train the Gated Recurrent Unit model based on the difference (delta) between consecutive memory accesses. Finally, using a GRU model with learned memory access patterns, the proposed data prefetcher predicts the memory address to be accessed next. We have compared the model with the multi-layer perceptron, but our prefetcher showed better results than the Multi-Layer Perceptron.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.5_6
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• pp.232-238
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• 2003

Traditional operating systems use a virtual memory to provide users with a bigger memory than a physical memory. The virtual memory augments the insufficient physical memory by the swap device. Since disks are usually used as the swap device, the cost of a page fault is relatively high compared to the access cost of the physical memory. Recently, numerous papers have investigated the Network RAM in order to exploit the idle memory in the network instead of disks. Since today's distributed systems are interconnected with high-performance networks, the network latency is far smaller than the disk access latency In this paper we design and implement the Network RAM using block device driver on Linux. This is the first implementation of the Network RAM on Linux. We propose the new reliability method to recover the page when the other workstation's memory is damaged. The system using the Network RAM as the swap device reduces the execution time by 40.3% than the system using the disk as the swap device. The performance results suggest that the new reliability method that use the processor more efficiently has the similar execution time with others, but uses smaller server memory and generates less message traffic than others.