• Information Systems Review
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• v.5 no.1
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• pp.97-111
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• 2003

With the spread of electronic commerce on the Internet, comparison shopping sites with agent technique are getting popular for the best shopping. However, most consumers are still spending much time to search for the best price through the sites because each of them may show a different price even for the same goods or a site does not show any information about specific goods. Additionally, the search for the best price of the goods like books and CDs may cause the system to be overloaded and the response time to be long due to an on-line real-time search. In this paper, we have designed and implemented a meta-search system for comparison shopping sites with a local database and memory cache to resolve the above problems. The proposed system collects and maintains the price information of popular goods among the comparison shopping sites using several software agents. The experimental results show that our system is an efficient meta-comparison shopping engine and reduces the latency of the response time with little overhead.

• The KIPS Transactions:PartA
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• v.11A no.7 s.91
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• pp.489-498
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• 2004

VLIW processor is considered to be an appropriate processor for the embedded system, provided with high performance and low power con-sumption due to its simple hardware structure. Unfortunately, the VLIW processor often suffers from high memory access latency due to the variable length of I-packets, which consist of independent instructions to be issued in parallel. It is because of the variable I-packet length that some I-packets must be placed over two cache blocks, which are called straddle I-packets, so that two cache accesses are required to fetch such I-packets. In this paper, an expansion buffer cache is proposed to improve not only the instruction fetch bandwidth, but also the power consumption of the I-cache with moderate hardware cost. The expansion buffer cache has a small expansion buffer containing a fraction of a straddle packet along with the main cache to reduce the additional cache accesses due to the straddle I-packets. With a great reduction in the cache accesses due to the straddle packets, the expansion buffer cache can achieve $5{\~}9{\%}$improvement over the conventional I-caches in the $Delay{\cdot}Power{\cdot}Area$ metric.

• Journal of Korea Multimedia Society
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• v.14 no.6
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• pp.835-848
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• 2011

In this paper, we propose a client server based distributed/parallel system to effectively visualize huge geographic data. The system consists of a web-based client GUI program and a distributed/parallel server program which runs on multiple PC clusters. To make the client program run on mobile devices as well as PCs, the graphical user interface has been designed by using JOGL, the java-based OpenGL graphics library, and sending the information about current available memory space and maximum display resolution the server can minimize the amount of tasks. PC clusters used to play the role of the server access requested geographic data from distributed disks, and properly re-sample them, then send the results back to the client. To minimize the latency happened in repeatedly access the distributed stored geography data, cache data structures have been maintained in both every nodes of the server and the client.

• Proceedings of the Korean Society for Cognitive Science Conference
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• 2005.05a
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• pp.151-153
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• 2005

We investigated the brain substrate of repetition priming on the implicit memory taskusing low-resolution electromagnetic tomography (LORETA) with high-density 128 channel EEG and individual MRI as a realistic head model. Thirteen right-handed, healthy subjects performed a word/nonword discrimination task, in which the words and nonwords were presented visually,and some of the words appeared twice with a lag of one or five items. All of the subjects exhibited repetition priming with respect to the behavioral data, in which a faster reaction time was observed to the repeated word (old word) than to the first presentation of the word (new word). The old words elicited more positive-going potentials than the new words, beginning at 200 ms and lasting until 500 ms post-stimulus. We conducted source reconstruction using LORETA at a latency of 400 ms with the peak mean global field potentials and used statistical parametric mapping for the statistical analysis. We found that the source elicited by the old words exhibited a statistically significant current density reduction in the left inferior frontal gyrus. This is the first study to investigate the generators of repetition priming using voxel-by-voxel statistical mapping of the current density with individual MRI and high-density EEG.

• Journal of Korean Neurosurgical Society
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• v.53 no.3
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• pp.139-144
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• 2013

Objective : Transient anterograde amnesia is occasionally observed in a number of conditions, including migraine, focal ischemia, venous flow abnormalities, and after general anesthesia. The inhalation anesthetic, isoflurane, is known to induce transient anterograde amnesia. We examined the involvement of brain-derived neurotrophic factor (BDNF) and its receptor tyrosine kinase B (TrkB) in the underlying mechanisms of the isoflurane-induced transient anterograde amnesia. Methods : Adult male Sprague-Dawley rats were divided into three groups : the control group, the 10 minutes after recovery from isoflurane anesthesia group, and the 2 hours after recovery from isoflurane anesthesia group (n=8 in each group). The rats in the isoflurane-exposed groups were anesthetized with 1.2% isoflurane in 75% nitrous oxide and 25% oxygen for 2 hours in a Plexiglas anesthetizing chamber. Short-term memory was determined using the step-down avoidance task. BDNF and TrkB expressions in the hippocampus were evaluated by immunofluorescence staining and western blot analysis. Results : Latency in the step-down avoidance task was decreased 10 minutes after recovery from isoflurane anesthesia, whereas it recovered to the control level 2 hours after isoflurane anesthesia. The expressions of BDNF and TrkB in the hippocampus were decreased immediately after isoflurane anesthesia but were increased 2 hours after isoflurane anesthesia. Conclusion : In this study, isoflurane anesthesia induced transient anterograde amnesia, and the expressions of BDNF and TrkB in the hippocampus might be involved in the underlying mechanisms of this transient anterograde amnesia.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.5
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• pp.365-369
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• 2009

Overlapping windows are generally used for queries to process continuous data streams. Nevertheless, existing approaches discussed join algorithms only for basic types of windows such as tumbling windows and tuple-driven windows. In this paper, we propose an efficient join algorithm for overlapping windows, which are considered as a more general type of windows. The proposed algorithm is based on an incremental window join. It focuses on producing join results continuously when the memory overflow frequently occurs. It consists of (1) a method to use both of the incremental and full joins selectively, (2) a victim selection algorithm to minimize latency of join processing and (3) an idle time professing algorithm. We show through our experiments that the selective use of incremental and full joins provides better performance than using one of them only.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.54-60
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• 2008

The bus architecture consists of a master initiating a communication transaction, a slave responding to the transaction, a arbiter selecting a master, a bridge connecting buses and so on. Recently this is more complicated and developed toward multi-bus architecture. In this paper, several cases of multi-shared bus architecture are discussed and in order to decrease the bridge latency, the architecture introducing a memory selector is proposed. Finally, a LCD controller using DMA master is integrated in this bus architecture that is verified due to RTL simulation and FPGA board test. DMA, LCD line buffer and SDRAM controller are normally operated in the timing simulation using ModelSim tool, and the LCD image is confirmed in the real FPGA board containing LCD panel.

• Journal of Korea Game Society
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• v.5 no.3
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• pp.39-47
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• 2005

Current rendering processors are organized mainly to process a triangle as fast as possible and recently parallel 3D rendering processors, which can process multiple triangles in parallel with multiple rasterizers, begin to appear. For high performance in processing triangles, it is desirable for each rasterizer have its own local pixel cache. However, the consistency problem may occur in accessing the data at the same address simulaneously by more than one rasterizer. In this paper, we propose a parallel rendering processor architecture resolving such consistency problem effectively. Moreover, the proposed architecture reduces the latency due to a pixel cache miss significantly. The experimental results show that proposed architecture achieves almost linear speedup at best case even in sixteen rasterizer

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6A
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• pp.555-561
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• 2002

In this paper, a new designed circuit of highly parallel multiplier using standard basis over $GF(2^m)$ is presented. Prior to construct the multiplier circuit, we provide the Vector Code Generate Module(VCGM) that generate each vector codes for multiplication. Using these VCGMs, we can get all vector codes necessary for operation and modular sum up each independent corresponding basis, respectively. Following the equations in this paper, we can design generalized multiplier to m. For the proposed circuit in this parer, we show the example in $GF(2^4)$ using VCGMs. In this paper, we build a multiplier with VCGMs, AND blocks, and EX-OR blocks. Therefore the proposed circuit is easy to generalize for m and advantageous for VLSI. Also, it need no memory element and the latency not less fewer then other circuit. We verify the proposed circuit by functional simulation and show its result. Finally, we compare the circuit composition with other works and show its result with a table.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.38-44
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• 2009

Bus system consists of several masters, slaves, arbiter and decoder in a bus. Master means the processor that performs data command like CPU, DMA, DSP and slave means the memory that responds the data command like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method bus system performance can be charged definitely. Fixed priority and round-robin are used in general arbitration method and TDMA and Lottery bus methods are proposed currently as the improved arbitration schemes. In this stuff, we proposed the score arbitration method and composed TLM algorithm. Also we analyze the performance compared with general arbitration methods through simulation. In the future, bus arbitration policy will be developed with the basis of the score arbitration method and improve the performance of bus system.