• Journal of Microbiology and Biotechnology
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• v.21 no.8
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• pp.874-883
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• 2011

Many studies have shown that the steamed root of Rehmannia glutinosa (SRG), which is widely used in the treatment of various neurodegenerative diseases in the context of Korean traditional medicine, is effective for improving cognitive and memory impairments. The purpose of this study was to examine whether SRG extracts improved memory defects caused by administering scopolamine (SCO) into the brains of rats. The effects of SRG on the acetylcholinergic system and proinflammatory cytokines in the hippocampus were also investigated. Male rats were administered daily doses of SRG (50, 100, and 200 mg/kg, i.p.) for 14 days, 1 h before scopolamine injection (2 mg/kg, i.p.). After inducing cognitive impairment via scopolamine administration, we conducted a passive avoidance test (PAT) and the Morris water maze (MWM) test as behavioral assessments. Changes in cholinergic system reactivity were also examined by measuring the immunoreactive neurons of choline acetyltransferase (ChAT) and the reactivity of acetylcholinesterase (AchE) in the hippocampus. Daily administration of SRG improved memory impairment according to the PAT, and reduced the escape latency for finding the platform in the MWM. The administration of SRG consistently significantly alleviated memory-associated decreases in cholinergic immunoreactivity and decreased interleukin-$1{\beta}$ (IL-$1{\beta}$) and tumor necrosis factor-${\alpha}$ (TNF-${\alpha}$) mRNA expression in the hippocampus. The results demonstrated that SRG had a significant neuroprotective effect against the neuronal impairment and memory dysfunction caused by scopolamine in rats. These results suggest that SRG may be useful for improving cognitive functioning by stimulating cholinergic enzyme activities and alleviating inflammatory responses.

• The Journal of the Korea Contents Association
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• v.15 no.4
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• pp.9-16
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• 2015

On modern operating systems such as Linux, virtual memory is a general way to provide a large address space to applications by using main memory and storage devices. Recently, storage devices have been improved in terms of latency and bandwidth, and it is expected that applications with large memory show high-performance if next-generation storage devices are considered. However, due to the overhead of virtual memory subsystem, the paging system can not exploit the performance of next-generation storage devices. In this study, we propose several optimization techniques to extend memory with next-generation storage devices. The techniques are to allocate block addresses of storage devices for write-back operations as well as to configure the system parameters, and we implement the techniques on Linux 3.14.3. Our evaluation through using multiple benchmarks shows that our system has 3 times (/24%) better performance on average than the baseline system in the micro(/macro)-benchmark.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.42-47
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• 2020

In OFDM-based very high-speed communication systems, FFT/IFFT processor should have several properties of low-area and low-power consumption as well as high throughput and low processing latency. Thus, radix-2k MDF (multipath delay feedback) architectures by adopting pipeline and parallel processing are suitable. In MDF architecture, the feedback memory which increases in proportion to the input signal word-length has a large area and power consumption. This paper presents a feedback memory size reduction method of radix-22 MDF IFFT processor for OFDM applications. The proposed method focuses on reducing the feedback memory size in the first two stages of MDF architectures since the first two stages occupy about 75% of the total feedback memory. In OFDM transmissions, IFFT input signals are composed of modulated data and pilot, null signals. In order to reduce the IFFT input word-length, the integer mapping which generates mapped data composed of two signed integer corresponding to modulated data and pilot/null signals is proposed. By simulation, it is shown that the proposed method has achieved a feedback memory reduction up to 39% compared to conventional approach.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.678-681
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• 2002

In this paper, we propose a block LMS algorithm using distributed arithmetic (BDA) and a multi-memory block structured BDA (MBDA). Moreover, we propose an effective VLSI architecture of adaptive digital filter using MBDA, and evaluate the sampling rate and output latency.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.283-286
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• 2000

One major drawback of conventional output buffered switches is that the speed of writing cells into output buffer should be N times faster than input link speed. This paper proposes a new output buffer switch that divides one output buffer into several buffers and virtually shares the divided buffers by using a distributor. The proposed switch makes it possible to reduce the memory speed. The proposed switch is evaluated in terms of the average cell latency compared with the input buffered switches which use the arbitration alogorithms, i.e., iSLIP or wrapped wave front arbiter(WWFA).

• Proceedings of the KAIS Fall Conference
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• 2011.12b
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• pp.668-670
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• 2011

본 논문에서는 고속 무선 데이터 전송을 위하여 멀티버스 구조 및 유연적인 데이터 버퍼시스템을 갖는 향상된 바이너리 CDMA에 시스템 설계에 관한 것이다. 개선된 바이너리 CDMA 시스템 구조는 제한된 리소스에서 시스템 버스의 Latency를 최대한 줄이고 고속 무선 데이터 전송을 위하여 버퍼접근구조를 변경하여 데이터 throughput을 향상하였다.

• The Transactions of the Korea Information Processing Society
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• v.7 no.3
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• pp.962-970
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• 2000

Multithreading is attractive in that it can tolerate memory latency and synchronization by effectively overlapping communication with computation. While several compiler techniques have been developed to produce multithreaded codes from functional languages programs, there still remains a lot of works to implement loops effectively. Executing lops in a style of multithreading usually causes some overheads, which can reduce severely the effect of multirheading. This paper suggests several methods in terms of architectures or compilers which can optimize loop execution by multithreading. We then simulate and analyze them for the matrix multiplication program.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.11a
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• pp.1035-1038
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• 2008

가상 메모리의 스왑 저장 장치로서 플래시 메모리를 사용하는 경우, 시스템을 기동할 때 스왑 영역의 초기화를 위한 삭제 연산이 요구되어 기동 시간이 오래 걸리는 문제점이 있다. 본 논문에서는 스왑 영역의 플래시 메모리 내용을 모두 삭제하지 않고 일부만을 삭제함으로서 기동 시간을 줄일 수 있는 방법을 연구하였다.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.527-528
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• 2008

In this paper, several cases of multi-shared bus architecture are discussed and in order to decrease the bridge latency, the architecture introducing a memory decoder is proposed. Finally, a LCD controller using DMA master is integrated in this bus architecture that is verified due to RTL simulation and FPGA board test. DMA, LCD line buffer and SDRAM controller are normally operated in the timing simulation using ModelSim tool, and the LCD image is confirmed in the real FPGA board containing LCD panel.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.106-111
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• 2023

The importance of load-to-use latency has been highlighted as state-of-the-art computing cores adopt deep pipelines and high clock frequencies. The cascaded cache was recently proposed to reduce the access cycle of the L1 cache by utilizing differences in latencies among banks of the cache structure. However, this study assumes the cache is comprised of SRAM, making it unsuitable for direct application to non-volatile memory-based systems. This paper proposes a novel mechanism and structure for lowering dynamic energy consumption. It inserts monitoring logic to keep track of swap operations and write counts. If the ratio of swap operations to total write counts surpasses a set threshold, the cache controller skips the swap of cache blocks, which leads to reducing write operations. To validate this approach, experiments are conducted on the non-volatile memory-based cascaded cache. The results show a reduction in write operations by an average of 16.7% with a negligible increase in latencies.