• The Transactions of the Korea Information Processing Society
• /
• v.6 no.5
• /
• pp.1351-1361
• /
• 1999

The wide spread of multimedia system demands a large area viewing display device which can inform a message to many people in open area. This paper is about the design of a large area viewing LED panel control system. The control system runs on 16 bit microprocessor MC68EC000 and has following functions: 16 line clock and time, 2 channel priority interrupt, 2 channel direct memory access, 2 channel 12 bit clock and timer, 2 channel infrared remocon receiver, 2 channel RS-232C with 16 byte FIFO, IBM PC/AT compatible keyboard interface, ISA bus, battery backuped real time clock, battery backuped 256 byte SRAM and watch dog timer. The core circuits are implemented to ASIC, considering lower cost, higher reliability, higher performance, smaller dimension, and lower power consumption. This is verified by simulation and fabricated in 0.6 um CMOS SOG processes. The total gate count is 39,083 and the clock frequency is 48 MGz. The fabricated ASIC is mounted on test board.

• Proceedings of the KIEE Conference
• /
• 1993.07a
• /
• pp.453-455
• /
• 1993

In this research, the digital signal processing PC board which employs TI's TMS320C25 is implemented. The board can perform following functions. spectrum analysis of speech and repetitive signal, digital filters emulation by convolution, signal generation of sinusoidal wave, rectangular wave etc.. In this system, communications between PC and DSP board. program down-loading to DSP board and recording and graphic of acquired and processed data in DSP board are executed by PC. Parallel interface and buffer memory are used in communications. Data acquisition and operation are carried out in DSP board. Resultant data are transmitted to PC and output through DAC.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.11a
• /
• pp.360-363
• /
• 2003

In this paper, we investigated SiNx film as a buffer layer of TFT-FRAM. Buffer layers were prepared by two step process of a $N_2$ plasma treatment and subsequent $SiN_x$ deposition. By employing $N_2$ plasma treatment, interface traps such as mobile charges and injected charges were removed, hysteresis of current-voltage curve disappeared. After $N_2$ plasma treatment, a leakage current was decreased about 2 orders. From these results, it is possible to perform the plasma treating process to make a good quality buffer layer of MFIS-FET or capacitor as an application of non-volatile memory.

• International Journal of Advanced Culture Technology
• /
• v.9 no.1
• /
• pp.196-202
• /
• 2021

Currently, as Korea enters into a fast aging society, the problem of dementia population is increasing. In this paper, we intend to contribute to the improvement of welfare for the elderly by developing virtual reality technology and related interface technology to effectively perform hand movements known as effective methods for preventing and treating dementia. As the content of the research and development of this paper, it is designed to be easy for the elderly to use and stimulate brain function by applying VR technology using sensors, and to activate mental and physical activities for the elderly who are marginalized in terms of cultural welfare. We intend to develop by classifying the types of games and contents that can induce them. As a result of this thesis, we developed contents using virtual reality to improve cognitive abilities for elderly people with poor cognitive ability to activate the brains of users' cognition, memory, and attention to prevent and treat dementia I want to contribute.

• Journal of information and communication convergence engineering
• /
• v.20 no.4
• /
• pp.295-302
• /
• 2022

This paper contains the development of a smart power device designed to collect load power data from industrial manufacturing machines, predict future variations in load power data, and detect abnormal data in advance by applying a machine learning-based prediction algorithm. The proposed load power data prediction model is implemented using a Long Short-Term Memory (LSTM) algorithm with high accuracy and relatively low complexity. The Flask and REST API are used to provide prediction results to users in a graphical interface. In addition, we present the results of experiments conducted to evaluate the performance of the proposed approach, which show that our model exhibited the highest accuracy compared with Multilayer Perceptron (MLP), Random Forest (RF), and Support Vector Machine (SVM) models. Moreover, we expect our method's accuracy could be improved by further optimizing the hyperparameter values and training the model for a longer period of time using a larger amount of data.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.12
• /
• pp.2202-2211
• /
• 2006

EXT3NS is a special-purpose file system for large scale multimedia streaming servers. It is built on top of streaming acceleration hardware device called Network-Storage card. The EXT3NS file system significantly improves streaming performance by eliminating memory-to-memory copy operations, i.e. sending video/audio from disk directly to network interface with no main memory buffering. In this paper, we design and implement a buffer cache mechanism, called PMEMCACHE, for EXT3NS file system. We also propose a buffer cache replacement method called ONS for the buffer cache mechanism. The ONS algorithm outperforms other existing buffer replacement algorithms in distributed multimedia streaming environment. In EXT3NS with PMEMCACHE, operation is 33MB/sec and random read operation is 2.4MB/sec. Also, the buffer replacement ONS algorithm shows better performance by 600KB/sec than other buffer cache replacement policies. As a result PMEMCACHE and an ONS can greatly improve the performance of multimedia steaming server which should supportmultiple client requests at the same time.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.7B
• /
• pp.605-619
• /
• 2003

The main memory DBMS(MMDBMS) efficiently supports various database applications that require high performance since it employs main memory rather than disk as a primary storage. In this paper, we discuss the index manager of the Tachyon, a next-generation MMDBMS. Recently, the gap between the CPU processing and main memory access times is becoming much wider due to rapid advance of CPU technology. By devising data structures and algorithms that utilize the behavior of the cache in CPU, we are able to enhance the overall performance of MMDBMSs considerably. In this paper, we address the practical implementation issues and our solutions for them obtained in developing the cache-conscious index manager of the Tachyon. The main issues touched are (1) consideration of the cache behavior, (2) compact representation of the index entry and the index node, (3) support of variable-length keys, (4) support of multiple-attribute keys, (5) support of duplicated keys, (6) definition of the system catalog for indexes, (7) definition of external APIs, (8) concurrency control, and (9) backup and recovery. We also show the effectiveness of our approach through extensive experiments.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.11
• /
• pp.86-94
• /
• 2012

In this paper we propose a hardware architecture of high-speed CGH (computer generated hologram) generation processor, which particularly reduces the number of memory access times to avoid the bottle-neck in the memory access operation. For this, we use three main schemes. The first is pixel-by-pixel calculation rather than light source-by-source calculation. The second is parallel calculation scheme extracted by modifying the previous recursive calculation scheme. The last one is a fully pipelined calculation scheme and exactly structured timing scheduling by adjusting the hardware. The proposed hardware is structured to calculate a row of a CGH in parallel and each hologram pixel in a row is calculated independently. It consists of input interface, initial parameter calculator, hologram pixel calculators, line buffer, and memory controller. The implemented hardware to calculate a row of a $1,920{\times}1,080$ CGH in parallel uses 168,960 LUTs, 153,944 registers, and 19,212 DSP blocks in an Altera FPGA environment. It can stably operate at 198MHz. Because of the three schemes, the time to access the external memory is reduced to about 1/20,000 of the previous ones at the same calculation speed.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.47 no.10
• /
• pp.36-42
• /
• 2010

FFT(Fast Fourier Transform) processor is one of the key components in the implementation of OFDM systems for many wireless standards such as IEEE 802.22. To improve the performances of FFT processors, various studies have been carried out to reduce the complexities of multipliers, memory interface, control schemes and so on. While the number of FFT stages increases logarithmically $log_2N$) as the FFT point-size (N) increases, the number of required registers (or, memories) increases linearly. In large point-size FFT designs, the registers occupy more than 70% of the chip area. In this paper, to reduce the memory size of IFFT for OFDM transmitters, we propose a new IFFT design method based on a combined mapping of modulated data, pilot and null signals. The proposed method focuses on reducing the sizes of the registers in the first two stages of the IFFT architectures since the first two stages require 75% of the total registers. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than 38.5% area reduction compared with previous IFFT designs.

• Transactions of the Korean Society of Mechanical Engineers
• /
• v.16 no.1
• /
• pp.122-131
• /
• 1992

An expert system is developed which can design the power transmission involute cylindrical gears on the basis of strength and durability. Bending strength, surface durability, scoring, and wear probability are considered as the basis. The basic components of the expert system are knowledge base, inference engine, and working memory. The knowledges in knowledge base are classified hierarchically into the knowledges used in selection of gear type, selection of materials, and determination of K factor and are represented by rules. In the inference engine two inference methods are implemented with the depth first search method. For-ward chaining method is introduced in the selection of gear type and materials and in the determination of K factor. Backward chaining method is introduced in the detailed design of module and face width in accordance with the validation of strength. And inference efficiency is achieved by constructing the part needing a lot of numerical calculations in strength estimation separately from inference mechanism. The working memory is established to save the results during inference temporarily. In addition, design database of past design results is built for consultation during design and knowledge acquisition facility, explanation facility, and user interface are included for the usefulness of user. This expert system is written with the PROLOG programming language and the FORTRAN language in numerical calculation part which interfaced with PROLOG and can also be executed on IBM-PC compatible computer operated by MS-DOS alone.