• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2534-2536
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• 2002

This paper presents the design of high speed bit and word processor for sequence logic control using a FPGA. This FPGA is able to execute sequence instruction during program fetch cycle, because the program memory was separated from the data memory for high speed execution at 40MHz clock. Also this processor has 274 instructions set with a 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by V600EHQ240 and Foundation tool of Xilinx company. The final simulation was successfully performed under Foundation tool simulation environment. And the FPGA programmed by VHDL for a 240 pin HQFP package. Finally the benchmark was performed to prove that the designed for bit and word processor has better performance than Q4A of Mitsubishi for the sequence logic control.

• Journal of Information Processing Systems
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• v.18 no.1
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• pp.159-172
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• 2022

The role of the interconnect network, which connects computing nodes to each other, is important in high-performance computing (HPC) systems. In recent years, the peripheral component interconnect express (PCIe) has become a promising interface as an interconnection network for high-performance and cost-effective HPC systems having the features of non-transparent bridge (NTB) technologies. OpenSHMEM is a programming model for distributed shared memory that supports a partitioned global address space (PGAS). Currently, little work has been done to develop the OpenSHMEM library for PCIe-interconnected HPC systems. This paper introduces a prototype implementation of the OpenSHMEM library through a switchless interconnect network using PCIe NTB to provide a PGAS programming model. In particular, multi-interrupt, multi-thread-based data transfer over the OpenSHMEM shared memory model is applied at the implementation level to reduce the latency and increase the throughput of the switchless ring network system. The implemented OpenSHMEM programming model over the PCIe NTB switchless interconnection network provides a feasible, cost-effective HPC system with a PGAS programming model.

• Journal of Internet Computing and Services
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• v.25 no.3
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• pp.1-8
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• 2024

As the Internet of Things (IoT) has gained significant prominence in our daily lives, most IoT devices rely on over-the-air technology to automatically update firmware or software remotely via the network connection to relieve the burden of manual updates by users. And preserving security for OTA interface is one of the main requirements to defend against potential threats. This paper presents a simulation of an attack scenario on the commoditized System-on-a-chip, ESP32 chip, utilized for drones during their OTA update process. We demonstrate three types of attacks, WiFi cracking, ARP spoofing, and TCP SYN flooding techniques and postpone the OTA update procedure on an ESP32 Drone. As in this scenario, unpatched IoT devices can be vulnerable to a variety of potential threats. Additionally, we review the chip to obtain traces of attacks from a forensics perspective and acquire memory forensic artifacts to indicate the SYN flooding attack.

• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.4
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• pp.31-40
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• 2019

This paper proposes an adaptive PCIe system for TI C66x DSPs. Conventionally, the PCIe system provided by the C66x is a system dependent on the structure in which the primary core writes an application to the DSP memory through the PCIe interface, then activate the secondary core. Due to the dependency between the cores, when developing a project using a PCIe interface, the remaining cores have to be programmed with a concern of the primary core used as the PCIe interface. Therefore, in order to de-couple the connections among the cores, an adaptive PCIe system is proposed, in the paper, in which the cores operate independently compared to the conventional system. Since the core used as the PCIe interface only runs PCIe related operations in the new system, the remaining cores can be fully utilized without concerning the connections with the core for PCIe interface. In order to verify the feasibility of the proposed adaptive PCIe system, the implementations of LTE-A down link, and IEEE 802.11ac are carried out using the evaluation board which includes a TMS320C6670 chip. Altogether, these results support that we demonstrated that the digital signal processing systems with the PCIe Interface can be developed more rapidly by applying the proposed system.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.211.2-211.2
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• 2014

Epitaxial complex oxide thin film heterostructures have attracted a great attention for their multifunctional properties, such as ferroelectricity, and ferromagnetism. Two dimensional electron gas (2DEG) confined at the interface between two insulating perovskite oxides such as LaAlO3/SrTiO3 interface, provides opportunities to expand various electronic and memory devices in nano-scale. Recently, it was reported that the conductivity of 2DEG could be controlled by external electric field. However, the switched conductivity of 2DEG was not stable with time, resulting in relaxation due to the reaction between charged surface on LaAlO3 layer and atmospheric conditions. In this report, we demonstrated a way to control the conductivity of 2DEG in non-volatile way integrating ferroelectric materials into LAO/STO heterostructure. We fabricated epitaxial Pb(Zr0.2Ti0.8)O3 films on LAO/STO heterostructure by pulsed laser deposition. The conductivity of 2DEG was reproducibly controlled with 3-order magnitude by switching the spontaneous polarization of PZT layer. The controlled conductivity was stable with time without relaxation over 60 hours. This is also consistent with robust polarization state of PZT layer confirmed by piezoresponse force microscopy. This work demonstrates a model system to combine ferroelectric material and 2DEG, which guides a way to realize novel multifunctional electronic devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.2
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• pp.106-110
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• 1998

The $LiNbO_3$ thin films were prepared directly on Si(100) substrates by conventional RF magnetron spurttering system for nonvolatile memory applications. RTA(Rapid Thermal Annealing) treatment was performed for as-deposited films in an oxygen atmosphere at 600 $^{\circ}C$ for 60 s. The rapid thermal annealed films were changed to poly-crystalline ferroelectric nature from amorphous of as-deposition. The resistivity of the ferroelectric $LiNbO_3$ film was increased from a typical value of $1{\sim}2{\times}10^8{\Omega}{\cdot}cm$ before the annealing to about $1{\times}10^{13}{\Omega}{\cdot}cm$ at 500 kV/cm and reduced the interface state density of the $LiNbO_3/Si$ (100) interface to about $1{\times}10^{11}/cm^2{\cdot}eV$. Ferroelectric hysteresis measurements using a Sawyer-Tower circuit yielded remanent polarization ($P_r$) and coercive field ($E_c$) values of about 1.2 ${\mu}C/cm^2$ and 120 kV/cm, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.331-331
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• 2012

With the NAND Flash scaling down, it becomes more and more difficult to follow Moore's law to continue the scaling due to physical limitations. Recently, three-dimensional (3D) flash memories have introduced as an ideal solution for ultra-high-density data storage. In 3D flash memory, as the process reason, we need to use poly-Si TFTs instead of conventional transistors. So, after combining charge trap flash (CTF) structure and poly-Si TFTs, the emerging device SONOS-TFTs has also suffered from some reliability problem such as hot carrier degradation, charge-trapping-induced parasitic capacitance and resistance which both create interface traps. Charge pumping method is a useful tool to investigate the degradation phenomenon related to interface trap creation. However, the curves for charge pumping current in SONOS TFTs were far from ideal, which previously due to the fabrication process or some unknown traps. It needs an optimization and the important geometrical effect should be eliminated. In spite of its importance, it is still not deeply studied. In our work, base-level sweep model was applied in SONOS TFTs, and the nonideal charge pumping current was optimized by adjusting the gate pulse transition time. As a result, after the optimizing, an improved charge pumping current curve is obtained.

• Electrical & Electronic Materials
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• v.10 no.10
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• pp.1029-1033
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• 1997

A prototype MFSFET using ferroelectric fluoride BaMgF$_4$as a gate insulator has been successfully fabricated with the help of 2 sheets of metal mask. The fluoride film was deposited in an ultrai-high vacuum system at a substrate temperature of below 30$0^{\circ}C$ and an in-situ post-deposition annealing was conducted for 20 seconds at $650^{\circ}C$ in the same chamber. The interface state density of the BaMgF$_4$/Si(100) interface calculated by a MFS capacitor fabricated on the same wafer was about 8$\times$10$^{10}$ /cm$^2$.eV. The I$_{D}$-V$_{G}$ characteristics of the MFSFET show a hysteresis loop due to the ferroelectric nature of the BaMgF$_4$film. It is also demonstrated that the I$_{D}$ can be controlled by the “write” plus which was applied before the measurements even at the same “read”gate voltage.ltage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.877-880
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• 2005

As DMB, 3D game, Internet and movie is serviced for the recent mobile devices, high resolution display devices beyond VGA become used. Implementation of real-time moving pictures of 30렌 by software programming is difficult because the performance of mobile processors is not so high. The full frame moving picture can be supported by using specific hardware. In this paper, an OLED controller that is consists of flash memory controller and OLED interface is proposed for real-time moving picture on mobile displays. The proposed OLED controller is implemented in FPGA and the performance is evaluated.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1295-1297
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• 1996

CCITT G.721, G.723 standard ADPCM algorithm is implemented by using TI's fixed point DSP start kit (DSK). ADPCM can be implemented on a various rates, such as 16K, 24K, 32K and 40K. The ADPCM is sample based compression technique and its complexity is not so high as the other speech compression techniques such as CELP, VSELP and GSM, etc. ADPCM is widely applicable to most of the low cost speech compression application and they are tapeless answering machine, simultaneous voice and fax modem, digital phone, etc. TMS320C50 DSP is a low cost fixed point DSP chip and C50 DSK system has an AIC (analog interface chip) which operates as a single chip A/D and D/A converter with 14 bit resolution, C50 DSP chip with on-chip memory of 10K and RS232C interface module. ADPCM C code is compiled by TI C50 C-compiler and implemented on the DSK on-chip memory. Speech signal input is converted into 14 bit linear PCM data and encoded into ADPCM data and the data is sent to PC through RS232C. The ADPCM data on PC is received by the DSK through RS232C and then decoded to generate the 14 bit linear PCM data and converted into the speech signal. The DSK system has audio in/out jack and we can input and out the speech signal.