• Proceedings of the Korea Society of Design Studies Conference
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• 2004.05a
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• pp.304-305
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• 2004

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.6
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• pp.391-397
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• 2015

Nonvolatile memories in memory hierarchy have been investigated to reduce its energy consumption because nonvolatile memories consume zero leakage power in memory cells. One of the difficulties is, however, that the endurance of most nonvolatile memory technologies is much shorter than the conventional SRAM and DRAM technology. This has limited its usage to only the low levels of a memory hierarchy, e.g., disks, that is far from the CPU. In this paper, we study the use of a new type of nonvolatile memories - the Phase Change Memory (PCM) with a DRAM buffer system as the main memory. Our design reduced the total energy of a DRAM main memory of the same capacity by 80%. These results indicate that it is feasible to use PCM technology in place of DRAM in the main memory for better energy efficiency.

• Journal of the Korean Institute of Intelligent Systems
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• v.11 no.4
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• pp.340-346
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• 2001

This paper proposes a new design method for the GBAM: (general bidirectional associative memory) model. Based on theoretical investigations on the GBAM: model, it is shown that the design of the GBAM:-based bidirectional associative memeories can be formulated as optimization problems called GEVPs (generalized eigenvalue problems). Since the GEVPs arising in the procedure can be efficiently solved within a given tolerance by the recently developed interior point methods, the design procedure established in this paper is very useful in practice. The applicability of the proposed design procedure is demonstrated by simple design examples considered in related studies.

• The Journal of Industrial Distribution & Business
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• v.12 no.5
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• pp.47-58
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• 2021

Purpose - Current research aimed at exploring the effect differences between the two types of processing product information such as the imagining and the considering on psychological product ownership which could influence the intent to purchase or use the product, and focused on identifying the interaction effects of activated memory information type and advertising information type on each of the information processing types. Research design, data, and methodology - This study divided the information processing types into imagining and considering, and the consumer's memories were divided into autobiographical or episodic and semantic memory. The advertising information was approached in each of event information being together with the product and product feature information. At empirical study, 2(two types of memory activation: episodic and semantic memory activation) ∗ 2(two types of advertising information: event-focused and product feature-focused advertising information) between-subjects design was used to make four types of questionnaire according to the type of experimental groups. Through the survey platform, 'questionnaire stars' of 'WeChat' in China, 219 questionnaire data were collected for empirical study. The structural equation model in AMOS 26 and Anova were used to verify hypotheses. Results - First, the ownership affected the usage intent positively. Second, the imagining did not affect the psychological ownership but did directly affect the usage intention, and the considering affected the ownership positively. Third, the episodic memory activation positively influenced the imagining and negatively affected the considering, whereas the semantic memory activation positively influenced the considering and negatively affected the imagining. Fourth, event-advertising information increased the effects of the activated episodic memory on the imagining, and feature-advertising information increased the effects of the activated semantic memory on the considering. Conclusions - marketers should develop and advertise their product-related event message to trigger the imaging that directly increase the intent to purchase or use their product, when consumers are under the activation of their episodic memory. And marketers should advertise their product feature-related message to trigger the considering that could induce consumers' ownership for their product to increase the intent to purchase or use their product, when they are under the activation of their semantic memory.

• ETRI Journal
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• v.35 no.5
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• pp.808-818
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• 2013

Programmable memory built-in self-test (PMBIST) is an attractive approach for testing embedded memory. However, the main difficulties of the previous works are the large area overhead and low flexibility. To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single-port memory and dual-port memory using various test algorithms is proposed. In the FPMBIST, a new instruction set is developed to minimize the FPMBIST area overhead and to maximize the flexibility. In addition, FPMBIST includes a diagnostic scheme that can improve the yield by supporting three types of diagnostic methods for repair and diagnosis. The experiment results show that the proposed FPMBIST has small area overhead despite the fact that it supports various test algorithms, thus having high flexibility.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.8
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• pp.2077-2089
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• 1996

In this paper, a memory organization and its control method are proposed for the implementation of parallel Virterbi decoders. The design is mainly focused on lowering the hardware complexity of a parallel Viterbi decoder which is to reduce the decoding speed. The memories requeired in a Viterbi decoder are the SMM(State Metric Memory) and the TBM(Traceback Memory);the SMM for storing the path metrics of states and the TBM for storing the survial path information. A general parallel Viterbi decoder for high datarate usually consists of multiple ACS (Add-Compare-Select) units and their corresponding memeory modules.for parallel ACS units, SMMs and TBMs are partitioned into smaller independent pairs of memory modules which are separately interleaved to provide the maximum processing speed. In this design SMMs are controlled with addrss generators which can simultaneously compute addresses of the new path metrics. A bit shuffle technique is employed to provide a parallel access to the TBMs to store the survivor path informations from multiple ACS modules.

• Transactions of the Society of Information Storage Systems
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• v.2 no.4
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• pp.214-218
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• 2006

The focus and tracking servo system has been designed and proposed for the holographic memory of one dimensional spatial light modulator(SLM). The general servo method of conventional ODD system was based and modified for new holographic memory. The pre-grooved disc pattern and special dichroic coating were also included for new design in this research and the final separated optics are expected to be applied to the future general holographic memory as well as the one dimensional SLM holographic memory.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.41 no.7
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• pp.784-792
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• 1992

In this paper we design and implement a method for application programs to allow handling of large data files in DOS environment. In this method we use extended memory and hard disk as a data buffer. And we use a part of the conventional DOS memory as a buffer cache which allows the application program to use extended memory and hard disks transparently. Using buffer cache also allows us some speed improvement for the application program.

• Proceedings of the Korea Information Processing Society Conference
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• 2020.11a
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• pp.12-15
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• 2020

Data access characteristics can directly affect the efficiency of the system execution. This research is to design an accurate predictor by using historical memory access information, where highly accessible data can be migrated from low-speed storage (SSD/HHD) to high-speed memory (Memory/CPU Cache) in advance, thereby reducing data access latency and further improving overall performance. For this goal, we design a locally weighted linear regression prefetch scheme to cope with irregular access patterns in large graph processing applications for a DARM-PCM hybrid memory structure. By analyzing the testing result, the appropriate structural parameters can be selected, which greatly improves the cache prefetching performance, resulting in overall performance improvement.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1209-1212
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• 2003

In this paper, we propose a SDRAM Controller. The SDRAM is often used a mainstream memory as embedded system memory due to its short latency, burst access and pipeline features. The proposed Controller provides essential functions for SDRAM initialization, read/write accesses, memory refresh and Burst access. Furthermore, the proposed controller is implemented in the form of SOFT IP. Therefore, it reduces the designer's effort greatly.