• 제어로봇시스템학회:학술대회논문집
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• 1990.10b
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• pp.1399-1404
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• 1990

There is an increasing need to apply artificial intelligence to the real application fields of industry. These include an intelligent process control, an expert machine and a diagnostic and/or maintenance machine. These applications are implemented in AI Languages. It is commonly recognized that AI Languages, such as Common Lisp or Prolog, require a workstation. This is mainly due to the fact that both languages need a large amount of memory space and disk storage space. Workstations are appropriate for a laboratory or office environment. However, they are too bulky to use in the real application fields of industry or business. Also users who apply artificial intelligence to these fields wish to have their own operating systems. We propose a new design method of an intelligent controller which is embedded within equipment and provides easy-to-use tools for artificial intelligence applications. In this paper we describe the new design method of a VMEbus based intelligent controller for artificial intelligence applications and a small operating system which supports Common Lisp and Prolog.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.04b
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• pp.235-240
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• 1995

In order to eliminate position errors existing at the steady state in the motion control of robotic manipulators, a new fuzzy control algorithm is proposed using three variables, position error, velocity error and integral of position errors as input variables of the fuzzy controller. Three dimensional look-up table is used toreduce the computational time in real-time control, and a technique reducing the amount of necessary memory is introduced. Simulation and experimental studies show that the position errors at the steady state are decreased more than 90% compared to those of existing fuzzy controller when the proposed fuzzy controller is applied to the 2 axis direct drive SCARA robot manipulator.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2002.12a
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• pp.113-117
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• 2002

PID controllers, which have been widely used in industry, have a simple structure and robustness to modeling error. But it is difficult to have uniformly good control performance in system parameters variation or different velocity command. In this paper, we propose a nonlinear adaptive PR controller based on an Immune feedback mechanism and a gradient descent teaming. This algorithm has a simple structure and robustness to system parameters variation. To verify performances of the proposed nonlinear adaptive PID controller, the speed control of nonlinear DC motor Is peformed. The simulation results show that the proposed control systems are effective in tracking a command velocity under system parameters variation

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.6
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• pp.7-16
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• 1984

This paper describes the overall procedure of the development of a digital audio response system. It has been developed specifically as an answering system to the inquiries of telephone numbers from subscribers. The system has been realized based on the residual excited linear prediction (RELP) algorithm that incorporates a pitch predictive loop. Its major advantage over other similar systems is that it produces high quality of synthetic speech, although its memory size is relatively small. The hardware which consists of a speech synthesizer, a controller and an I/O part has been constructed using 2900 series bit-slice microprocessors and an INTEL 8085 microprocessor. The system is capable of real time processing, reliable, and adaptable to other applications.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.2
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• pp.55-61
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• 2013

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). Contemporary FPGAs have large resources of logic gates and RAM blocks to implement complex digital computations. In this paper, we implement a system of digital instrumentation using FPGA. This system consists of the trigger part, memory address controller part, control FSM part, Encoder part, LCD controller part. The hardware implement using FPGA and the verification of the operation is done in a PC simulation. The proposed hardware was mapped into Cyclone III EP2C5Q208 from Altera and used 1,700(40%) of Logic Element (LE). The implemented circuit used 24,576-bit memory element with 6-bit input signal. The result from implementing in hardware (FPGA) could operate stably in 140MHz.

• Journal of the Korean Institute of Intelligent Systems
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• v.8 no.3
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• pp.9-15
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• 1998

This paper presents an adaptive learning control method for unknown nonlinear systems by combining neuro control and iterative learning control techniques. In the present control system, an iterative learning controller (ILC) is used for a process of short term memory involved in a temporary adaptive and learning manipulation and a short term storage of a specific temporary action. The learning gain of the iterative learning law is estimated by using a neural network for an unknown system except relative degrees. The control informations obtained by ILC are transferred to a long term memory-based feedforward neuro controller (FNC) and accumulated in it in addition to the previously stored infonnations. This scheme is applied to a two link robot manipulator through simulations.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.26 no.1
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• pp.196-202
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• 2002

In this work, we propose a new type of HDD suspension featuring shape memory alloy (SMA) actuator in order to prevent the contact between the slider and disk. The principal design parameters are obtained from the modal analysis using finite element analysis, and then the dynamic model is established to formulate the control scheme for Non-Contact Start/stop mode drive. Subsequently, a robust H$\_$$\infty$/ control algorithm is designed by integrating experimentally-Obtained SMA actuator dynamics to the proposed HDD suspension system. The controller is empirically realized and control results for the load/unload profiles are presented in time domain. In addition, the contact signal between the slider and disk is measured by the electrical resistance method.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.188-198
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• 2013

In order to increase its performance, NAND flash memory-based storage is composed of data buses that are shared by a number of flash memories and uses a parallel technique that can carry out multiple flash memory operations simultaneously. Since the storage performance is strongly influenced by the performance of each data bus, it is important to improve the utilization of the bus by ensuring effective scheduling of operations by the storage controller. However, this is difficult because of dynamic changes in buses due to the unique characteristics of each operation with different timing, cost, and usage by each bus. Furthermore, the scheduling technique for increasing bus utilization may cause unanticipated operation delay and wastage of storage resource. In this study, we suggest various dynamic operation scheduling techniques that consider data bus performance and storage resource efficiency. The proposed techniques divide each operation into three different stages and schedule each stage depending on the characteristics of the operation and the dynamic status of the data bus. We applied the suggested techniques to the controller and verified them on the FPGA platform, and found that program operation decreased by 1.9% in comparison to that achieved by a static scheduling technique, and bus utilization and throughput was approximately 4-7% and 4-19% higher, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.2
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• pp.126-130
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• 2006

Programmable Logic Controller(PLC) is the most widely utilized and plays an important role in industrial control system. Sequential Function Chart(SFC) is a graphic language which is suitable for describing a sequential control logic in discrete control system. We can design a distribute control construction and a hierarchical control construction in process control system described by SFC. In hierarchical control structure, we construct each subsystems to synchronize a synchronous signal between subsystems, and the command system gives and takes a synchronous signal with subsystems. Therefore, the system has a low memory efficiency and a low system performance. In this paper, we propose the method that improved the efficiency of memory in hierarchical control construction, and confirm its feasibility through an actual example.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.3
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• pp.837-852
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• 2021

Recurrent neural network (RNN) architectures have been used for language modeling (LM) tasks that require learning long-range word or character sequences. However, the RNN architecture is still suffered from unstable gradients on long-range sequences. To address the issue of long-range sequences, an attention mechanism has been used, showing state-of-the-art (SOTA) performance in all LM tasks. A differentiable neural computer (DNC) is a deep learning architecture using an attention mechanism. The DNC architecture is a neural network augmented with a content-addressable external memory. However, in the write operation, some information unrelated to the input word remains in memory. Moreover, DNCs have been found to perform poorly with low numbers of weight parameters. Therefore, we propose a robust memory deallocation method using a limited retention vector. The limited retention vector determines whether the network increases or decreases its usage of information in external memory according to a threshold. We experimentally evaluate the robustness of a DNC implementing the proposed approach according to the size of the controller and external memory on the enwik8 LM task. When we decreased the number of weight parameters by 32.47%, the proposed DNC showed a low bits-per-character (BPC) degradation of 4.30%, demonstrating the effectiveness of our approach in language modeling tasks.