• Structural Engineering and Mechanics
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• v.22 no.2
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• pp.241-262
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• 2006

NiTi-wire shape memory alloy (SMA) dampers, that utilize NiTi SMA wires to simultaneously damp tension, compression and torsion, was developed for structural control implementation in this study. First, eight reduced-scale NiTi-wire SMA dampers were constructed. Then tension, compression and torsion experiments using the eight reduced-scale NiTi-wire SMA dampers of different specification were done. The experimental results revealed all of the eight reduced-scale NiTi-wire SMA dampers had the ability to simultaneously supply tension-compression damping and torsion damping. Finally, mechanics analysis of the NiTi-wire SMA dampers was done based on a model of the SMA-wire restoring force and on tension-compression and torsion damping analysis. The damping analytical results were found to be similar to the damping experimental results.

• Journal of Information Display
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• v.12 no.2
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• pp.77-83
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• 2011

The memory compression algorithm CCC-LCP (color-count-controlled local color palette) reduces flicker in the liquid crystal display (LCD) overdrive. Its compression ratio is 1:5.4 for 10-bit images, with a 33 dB PSNR peak signal-to-noise ratio and with five times flicker reduction compared with the block truncation coding. The authors' two-alternative forced choice subjective tests proposed two new soundness properties, the 'CMP harmlessness' and 'OD non-lost (or OD liveliness)', to clarify the functional interaction between the overdrive functionality OD and the compression functionality CMP. The tests verified that CCC-LCP is practically applicable (at a 1.2H viewing distance threshold) for 42" 37-ppi WXGA TVs.

• Journal of the Korea Society of Computer and Information
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• v.25 no.4
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• pp.1-9
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• 2020

In this paper, we propose Dynamic Rank Subsetting (DRAS) technique that enhances the energy-efficiency and the performance of memory system through the data compression. The goal of this technique is to enable a partial chip access by storing data in a compressed format within a subset of DRAM chips. To this end, a memory rank is dynamically configured to two independent sub-ranks. When writing a data block, it is compressed with a data compression algorithm and stored in one of the two sub-ranks. To service a memory request for the compressed data, only a sub-rank is accessed, whereas, for a memory request for the uncompressed data, two sub-ranks are accessed as done in the conventional memory systems. Since DRAS technique requires minimal hardware modification, it can be used in the conventional memory systems with low hardware overheads. Through experimental evaluation with a memory simulator, we show that the proposed technique improves the performance of the memory system by 12% on average and reduces the power consumption of memory system by 24% on average.

• Journal of KIISE
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• v.44 no.7
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• pp.658-667
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• 2017

The demand for large-scale storage systems has continued to grow due to the emergence of multimedia, social-network, and big-data services. In order to improve the response time and reduce the load of such large-scale storage systems, DRAM-based in-memory cache systems are becoming popular. However, the high cost of DRAM severely restricts their capacity. While the method of compressing cache entries has been proposed to deal with the capacity limitation issue, compression and decompression, which are technically difficult to parallelize, induce significant processing overhead and in turn retard the response time. A selective compression scheme is proposed in this paper for in-memory file system caches that rapidly estimates the compression ratio of incoming cache entries with their Shannon entropies and compresses cache entries with low compression ratio. In addition, a description is provided of the design and implementation of an in-kernel in-memory file system cache with the proposed selective compression scheme. The evaluation showed that the proposed scheme reduced the execution time of benchmarks by approximately 18% in comparison to the conventional non-compressing in-memory cache scheme. It also provided a cache hit ratio similar to the all-compressing counterpart and reduced 7.5% of the execution time by reducing the compression overhead. In addition, it was shown that the selective compression scheme can reduce the CPU time used for compression by 28% compared to the case of the all-compressing scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.41-52
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• 2009

In Motion JPEG2000 encoding, huge bandwidth requirement of data memory access is the bottleneck in required system performance. For the alleviation of this bandwidth requirement, a new embedded compression(EC) algorithm with a little bit of image quality drop is devised. For both random accessibility and low latency, very simple and efficient entropy coding algorithm is proposed. We achieved significant memory bandwidth reductions (about 53${\sim}$81%) and reduced code-block memory to about half size through proposed multi-mode algorithms, without requiring any modification in JPEG2000 standard algorithm.

• The Journal of the Acoustical Society of Korea
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• v.41 no.1
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• pp.64-69
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• 2022

Background music is presented simultaneously with target messages. The main content should be kept intact for some time to aid decision making process. The maintenance of this information requires auditory working memory. The temporal compression of background music may often adopted due to the limitation of the presentation time. In this study, auditory working memory and decision making proces were analyzed in terms of temporal compression ratios of the background music. A total of 37 subjects of early twenties joined the study. Selected products were categorized based on eigen values of multi-dimensional scaling. Four presentation conditions were cases with no background music, background music with no compression, background music with low compression, and background music high compression. Matched reponses were analyzed through repeated ANOVA. Results showed that the high involvement product required more working memory resources. However, the increased level of usage did not always lead to the corresponding changes in decision making process. This approach may be useful in analyzing the role of time compression and working memory in consumer behaviors.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.3
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• pp.177-184
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• 2017

High performance non-volatile memory system can mitigate the gap between main memory and storage. However, no single memory devices fulfill the requirements. Non-volatile Dual In-line Memory Module (NVDIMM) consisted of DRAMs and NAND Flashes has been proposed to achieve the performance and non-volatility simultaneously. When power outage occurs, data in DRAM is backed up into NAND Flash using a small-size external energy storage such as a supercapacitor. Backup and restore operations of NVDIMM do not cooperate with the operating system in the NVDIMM standard, thus there is room to optimize its operation. This paper analysis the operation of NVDIMM and proposes a method to reduce backup and restore time. Particularly, data compression is introduced to reduce the amount of data that to be backed up and restored. The simulation results show that the proposed method reduces up to 72.6% of backup and restore time.

• Journal of Korea Game Society
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• v.14 no.6
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• pp.59-68
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• 2014

Memory bandwidth requirements of UHD (Ultra High Definition $4096{\times}2160$) game scenes have been much more increasing. This paper presents a lossless DPCM-GR based compression algorithm using CUDA for solving the memory bandwidth problem without sacrificing image quality, which is modified from DDPCM-GR [4] to support bit parallel pipelining. The memory bandwidth efficiency increases because of using the shared memory of CUDA. Various asynchronous transfer configurations which can overlap the kernel execution and data transfer between host and CUDA are implemented with the page-locked host memory. Experimental results show that the maximum 31.3 speedup is obtained according to CPU time. The maximum 30.3% decreases in the computation time among various configurations.

• The KIPS Transactions:PartB
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• v.10B no.5
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• pp.575-578
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• 2003

SPIHT algorithm is a wavelet based fast and effective technique for image compression. It uses a list structure to store status information which is generated during set-partitioning of zero-tree. Usually, this requires lots of additional memory depending on how high the bit-rate is. Therefore, in this paper, we propose a new technique called MZP-DFS, which needs no additional memory when running SPIHT algorithm. It traverses a spatial-tree according to DFS and eliminates additional memory as it uses test-functions for encoding and LSB bits of coefficients for decoding respectively. This method yields nearly the same performance as SPIHT. This may be desirable in hardware implementation because no additional memory is required. Moreover. it exploits parallelism to process each spatial-tree that it can be applied well in real-time image compression.

• Journal of Korea Multimedia Society
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• v.14 no.7
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• pp.917-923
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• 2011

In this paper, a new prediction based embedded compression (EC) codec algorithm for the JPEG2000 encoder system is proposed to reduce excessive memory requirements. The EC technique can reduce the 50 % memory requirement for intermediate low-frequency coefficients during multiple discrete wavelet transform (DWT) stages compared with direct implementation of the DWT engine of this paper. The LOCO-I predictor and MAP are widely used in many lossless picture compression codec. The proposed EC algorithm use these predictor which are very simple but surprisingly effective. The predictive EC scheme adopts a forward adaptive quantization and fixed length coding to encoding the prediction error. Simulation results show that our LOCO-I and MAP based EC codecs present only PSNR degradation of 0.48 and 0.26 dB in average, respectively. The proposed algorithm improves the average PSNR by 1.39 dB compared to the previous work in [9].