• Journal of the Korea Society of Computer and Information
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• v.20 no.7
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• pp.9-16
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• 2015

This paper proposes the parallel design of a shot change detection algorithm using frame segmentation and moving blocks. In the proposed approach, the high parallel processing components, such as frame histogram calculation, block histogram calculation, Otsu threshold setting function, frame moving operation, and block histogram comparison, are designed in parallel for NVIDIA GPU. In order to minimize memory access delay time and guarantee fast computation, the output of a GPU kernel becomes the input data of another kernel in a pipeline way using the shared memory of GPU. In addition, the optimal sizes of CUDA processing blocks and threads are estimated through the prior experiments. In the experimental test of the proposed shot change detection algorithm, the detection rate of the GPU based parallel algorithm is the same as that of the CPU based algorithm, but the average of processing time speeds up about 6~8 times.

• Nuclear Engineering and Technology
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• v.55 no.7
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• pp.2516-2533
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• 2023

Several practical methods for accelerating the depletion calculation in a GPU-based Monte Carlo (MC) code PRAGMA are presented including the multilevel spectral collapse method and the vectorized Chebyshev rational approximation method (CRAM). Since the generation of microscopic reaction rates for each nuclide needed for the construction of the depletion matrix of the Bateman equation requires either enormous memory access or tremendous physical memory, both of which are quite burdensome on GPUs, a new method called multilevel spectral collapse is proposed which combines two types of spectra to generate microscopic reaction rates: an ultrafine spectrum for an entire fuel pin and coarser spectra for each depletion region. Errors in reaction rates introduced by this method are mitigated by a hybrid usage of direct online reaction rate tallies for several important fissile nuclides. The linear system to appear in the solution process adopting the CRAM is solved by the Gauss-Seidel method which can be easily vectorized on GPUs. With the accelerated depletion methods, only about 10% of MC calculation time is consumed for depletion, so an accurate full core cycle depletion calculation for a commercial power reactor (BEAVRS) can be done in 16 h with 24 consumer-grade GPUs.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1553-1555
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• 1999

Recently, $SrBi_2Ta_2O_9$(SBT) and $Pb(ZrTi)O_3$(PZT) were much attracted as materials of capacitor for ferroelectric random access memory(FRAM) showing higher read/write speed, lower power consumption and nonvolartility. Bi-layered SBT thin film has appeared as the most prominent fatigue free and low operation voltage for use in nonvolatile memory. To highly integrate FRAM, SBT thin film should be etched. A lot of papers on SBT thin film and its characteristics have been studied. However, there are few reports about SBT thin film due to difficulty of etching. In order to investigate properties of etching of SBT thin film, SBT thin film was etched in $CF_4$/Ar gas plasma using magnetically enhanced inductively coupled plasma (MEICP) system. When $CF_4/(CF_4+Ar)$ is 0.1, etch rate of SBT thin film was $3300{\AA}/min$, and etch rate of Pt was $2495{\AA}/min$. Selectivities of SBT to Pt. $SiO_2$ and photoresist(PR) were 1.35, 0.6 and 0.89, respectively. With increasing $CF_4$ gas, etch rate of SBT thin film and $P_t$ decreased.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1260-1263
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• 2005

Data storage related with writing and retrieving requires high storage capacity, fast transfer rate and less access time. Today any data storage system cannot satisfy these conditions, however holographic data storage system can perform faster data transfer rate because it is a page oriented memory system using volume hologram in writing and retrieving data. System can be constructed without mechanical actuating part therefore fast data transfer rate and high storage capacity about 1Tb/cm3 can be realized. In this research, to reduce errors of binary data stored in holographic data storage system, a new method for bit error reduction is suggested. First, find fuzzy rule using experimental system for Element of Holographic Digital Data System. Second, make fuzzy rule table using Genetic algorithm. Third, reduce prior error element and recording Digital Data. Recording ratio and reconstruction ratio will be very good performance

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.3
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• pp.111-115
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• 2006

We investigated accelerated soft error rate(ASER) in 8M static random access memory(SRAM) cells. The effects on ASER by well structure, operational voltage, and cell transistor threshold voltage are examined. The ASER decreased exponentially with respect to operational voltage. The chips with buried nwell1 layer showed lower ASER than those either with normal well structure or with buried nwell1 + buried pwell structure. The ASER decreased as the ion implantation energy onto buried nwell1 changed from 1.5 MeV to 1.0 MeV. The lower viscosity of the capping layer also revealed lower ASER value. The decrease in the threshold voltage of driver or load transistor in SRAM cells caused the increase in the transistor on-current, resulting in lower ASER value. We confirmed that in order to obtain low ASER SRAM cells, it is necessary to also the buried nwell1 structure scheme and to fabricate the cell transistors with low threshold voltage and high on-current.

• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.44-46
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• 2005

Data storage related with writing and retrieving requires high storage capacity, fast transfer rate and less access time. Today any data storage system cannot satisfy these conditions, however holographic data storage system can perform faster data transfer rate because it is a page oriented memory system using volume hologram in writing and retrieving data. System can be constructed without mechanical actuating part therefore fast data transfer rate and high storage capacity about $1Tb/cm^3$ can be realized. In this paper, to reduce errors of binary data stored in holographic data storage system, a new method for bit error reduction is suggested. We proposal Algorithm use The Extended Kalman filter. The Kalman filter reduce measurement noise. Therefore, By using this error reduction method following results are obtained; the effect of measurement nois of Pixel is decreased and the intensity profile of data page becomes uniform therefore the better data storage system can be constructed.

• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.129-133
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• 2005

Data storage related with writing and retrieving requires high storage capacity, fast transfer rate and less access time. Today any data storage system cannot satisfy these conditions, however holographic data storage system can perform faster data transfer rate because it is a page oriented memory system using volume hologram in writing and retrieving data. System can be constructed without mechanical actuating part therefore fast data transfer rate and high storage capacity about $1Tb/cm^3$ can be realized. In this paper, to reduce errors of binary data stored in holographic data storage system, a new method for bit error reduction is suggested. First, find cluster centers using subtractive clustering algorithm then reduce intensities of pixels around cluster centers and fuzzy rules. Therefore, By using this error reduction method following results are obtained ; the effect of Inter Pixel Interference noise is decreased and the intensity profile of data page becomes uniform therefore the better data storage system can be constructed.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.685-691
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• 1993

This paper introduces a PC-based image data processing unit that is composed of preprocessor board and main processor board; The preprocessor contains Inmos A110 processor and efficient H/W architecture for fast mask/logic operations at the speed of video signal rate. It is controlled by the main processor which communicates with the host PC. The main processor board contains TI TMS320C31 digital signal processor, and can access the frame memory of the processor for extra S/W tasks. We test 3*3, 5*5 masks and logic operations on 386/486/DSP and compare the result with that of the proposed unit. The result shows ours are extremely faster than conventional CPU based approach, that is, over several hundred times faster than even DSP.

• Journal of Astronomy and Space Sciences
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• v.33 no.3
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• pp.229-236
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• 2016

We present proton-induced single event effects (SEEs) and γ-ray-induced total ionizing dose (TID) data for 1 Gbit lowpower double data rate synchronous dynamic random access memory (LPDDR SDRAM) fabricated on a 5 μm epitaxial layer (54 nm complementary metal-oxide-semiconductor (CMOS) technology). We compare our radiation tolerance data for LPDDR SDRAM with those of general DDR SDRAM. The data confirms that our devices under test (DUTs) are potential candidates for space flight applications.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.101-102
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• 2006

PZT thin films, which are the representative ferroelectric materials in ferroelectric random access memory (FRAM), have some serious problem such as the imprint, retention and fatigue which ferroelectric properties are degraded by repetitive polarization. BL T thin film capacitors were fabricated by plasma etching, however, the plasma etching of BLT thin film was known to be very difficult. In our previous study, the ferroelectric materials such as PZT and BLT were patterned by chemical mechanical polishing (CMP) using damascene process to top electrode/ferroelectric material/bottom electrode. It is also possible to pattern the BLT thin film capacitors by CMP, however, the CMP damage was not considered in the experiments. The properties of BLT thin films were changed by the change of polishing pressure although the removal rate was directly proportional to the polishing pressure in CMP process.