• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.1
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• pp.105-113
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• 1998

A new image processor is implemented for high-speed digital copiers and facsimiles. The imgage processor performs CCD and CIS interface, pre-processing, enlargement andreduction of gray level image, and various halftoning algorithms. Implemented halftoning algorithms are simple thresholding, fuzzy based mixed mode thresholding, dithering, and edge enhanced error diffusion. The result of binarization is transferred to a printer with serial or paralel output ports. Line by line pipelined data prodessing architecture is employed with time sharing access of the external memory. In receiving mode, it converts the resolution of received binary image for compatibility with conventional facsimile. In copy mode, a line of A3 paper with 400 dpi is processed with in 2.5 ms. The prototype of image processor was implemented usig Laser Programmable Gate Array (LPGA) with 0.8.mu.m technology.

• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.83-87
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• 2005

Data storage related with writing and retrieving requires high storage capacity, fast transfer rate and less access time in. Today any data storage system can not satisfy these conditions, but holographic data storage system can perform faster data transfer rate because it is a page oriented memory system using volume hologram in writing and retrieving data. System architecture without mechanical actuating pare is possible, so fast data transfer rate and high storage capacity about 1Tb/cm3 can be realized. In this paper, to correct errors of binary data stored in holographic digital data storage system, find cluster centers using clustering algorithm and reduce intensities of pixels around centers. We archive the procedure by two algorithms of C-mean and subtractive clustering, and compare the results of the two algorithms. By using proper clustering algorithm, the intensity profile of data page will be uniform and the better data storage system can be realized.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.11
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• pp.51-62
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• 2003

This paper presents a novel survivor memeory management and decoding techniques with sequential backward state transition control in the trace back Viterbi decoder. The Viterbi algorithm is an maximum likelihood decoding scheme to estimate the likelihood of encoder state for channel error detection and correction. This scheme is applied to a broad range of digital communication such as intersymbol interference removing and channel equalization. In order to achieve the area-efficiency VLSI chip design with high throughput in the Viterbi decoder in which recursive operation is implied, more research is required to obtain a simple systematic parallel ACS architecture and surviver memory management. As a method of solution to the problem, this paper addresses a progressive decoding algorithm with sequential backward state transition control in the trace back Viterbi decoder. Compared to the conventional trace back decoding techniques, the required total memory can be greatly reduced in the proposed method. Furthermore, the proposed method can be implemented with a simple pipelined structure with systolic array type architecture. The implementation of the peripheral logic circuit for the control of memory access is not required, and memory access bandwidth can be reduced Therefore, the proposed method has characteristics of high area-efficiency and low power consumption with high throughput. Finally, the examples of decoding results for the received data with channel noise and application result are provided to evaluate the efficiency of the proposed method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4A
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• pp.473-478
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• 2008

WAVE is a short-to-medium range communication standard that supports both public safety and private operations in roadside-to-vehicle and vehicle-to-vehicle communication environments. The core technology of physical layer in WAVE is orthogonal frequency division multiplexing (OFDM), which is sensitive to timing synchronization error. Besides, minimizing the latency in communication link is an essential characteristic of WAVE system. In this paper, a robust, low-complexity and small-latency timing synchronization algorithm suitable for WAVE system and its efficient hardware architecture are proposed. The comparison between proposed algorithm and other algorithms in terms of computational complexity and latency has shown the advantage of the proposed algorithm. The proposed architecture does not require RAM (Random Access Memory) which can affect the pipe lining ability and high speed operation of the hardware implementation. Synchronization error rate (SER) evaluation using both Matlab and FPGA implementation shows that the proposed algorithm exhibits a good performance over the existing algorithms.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.59-67
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• 2013

Reed-Solomon (RS) codes are powerful error-correcting codes used in diverse applications. Recently, algebraic soft-decision decoding algorithm for RS codes that can correct the errors beyond the error correcting bound has been proposed. The algorithm requires very intensive computations for interpolation, therefore an efficient VLSI architecture, which is realizable in hardware with a moderate hardware complexity, is mandatory for various applications. In this paper, we propose an efficient architecture with low hardware complexity for interpolation in soft-decision list decoding of Reed-Solomon codes. The proposed architecture processes the candidate polynomial in such a way that the terms of X degrees are processed in serial and the terms of Y degrees are processed in parallel. The processing order of candidate polynomials adaptively changes to increase the efficiency of memory access for coefficients; this minimizes the internal registers and the number of memory accesses and simplifies the memory structure by combining and storing data in memory. Also, the proposed architecture shows high hardware efficiency, since each module is balanced in terms of latency and the modules are maximally overlapped in schedule. The proposed interpolation architecture for the (255, 239) RS list decoder is designed and synthesized using the DongbuHitek $0.18{\mu}m$ standard cell library, the number of gate counts is 25.1K and the maximum operating frequency is 200 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.29-36
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• 2003

In this paper, an efficient VLSI architecture for DCTQ module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the module is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling 30 frame CIF image for both encoder and decoder simultaneously. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. To reduce the power consumption of DCTQ modu1e, we propose the method not to operate the DCTQ modu1e exploiting the SAE(sum of absolute error) value from motion estimation and cbp(coded block pattern). To reduce the AC/DC prediction memory size, the memory architecture and memory access method for AC/DC prediction block is proposed. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27MHz clock. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.417-418
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• 2006

CATIA V5 is one of the most preferred softwares in product design for domestic and industrial use. But with the development of the IT industry, design data by CATIA V5 can easily be hacked and stolen especially via the internet and through assistance storage medium. The design data could be protected through executive, physical and technical security system. The best way to maintain confidentiality of data from unauthorized access is to have a cryptosystem of the technical security. In this paper, a cryptosystem for the protection of design data was being proposed. The memory contains the file information made by the New and Open function of CATIA V5. No error can be expected even if the file changed before of after the application of Save and Open function, A cryptosystem was constructed in CATIA V5 by inserting crypto algorithm before and after the I/O process. The encryption/decryption algorithm of each function was based on the complex cipher, which applied permutation cipher and transpose cipher. The file security system was programmed in CAA V5 and Visual C++.

• Journal of the Korean Society for Precision Engineering
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• v.24 no.5
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• pp.77-81
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• 2007

CATIA V5 is one of the most preferred softwares in product design for domestic and industrial use. But with the development of the IT industry, design data by CATIA V5 can easily be hacked and stolen especially via the internet and through assistance storage medium. The design data could be protected through executive, physical and technical security system. the best way to maintain confidentiality of data from unauthorized access is to have a cryptosystem of the technical security. In this paper, a cryptosystem for the protection of design data was being proposed. The memory contains the file information made by the New and Open function of CATIA V5. No error can be expected even if the file changed before of after the application of Save and Open function. A cryptosystem was constructed in CATIA V5 by inserting crypto algorithm before and after the I/O process. The encryption/decryption algorithm of each function was based on the complex cipher, which applied permutation cipher and transpose cipher. The file security system was programmed in CAA V5 and Visual C++.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.92-99
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• 2005

In this paper, we present a high-level design methodology applied on a network system-on-a-chip(SOC) using SystemC. The main target of our approach is to get optimum performance parameters for high network address translation(NAT) throughput. The Fast Ethernet media access controller(MAC) and its direct memory access(DMA) controller are modeled with SystemC in transaction level. They are calibrated through the cycle-based measurement of the operation of the real Verilog register transfer language(RTL). The NAT throughput of the model is within $\pm$10% error compared to the output of the real evaluation board. Simulation speed of the model is more than 100 times laster than the RTL. The validated models are used for intensive architecture exploration to find the performance bottleneck in the NAT router.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6A
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• pp.341-350
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• 2003

In this paper, we evaluate the performance of a moving average (MA) channel estimation filter when space-time block coding transmit diversity (STBC-TD) is applied to the wideband direct sequence code division multiple access (WCDMA) forward link. And we present the infinite impulse response (IIR) filter scheme that can reduce the required memory buffer and the channel estimation delay time. This paper also compares the performance between MA filter scheme and IIR filter scheme in various Rayleigh fading channel environments through the bit error rate (BER) and the frame error rate (FER). Extensive computer simulation results show that transmission with STBC-TD provides a significant gain in performance over no transmit diversity technique, particularly at pedestrian speeds. If STBC-TD technique is employed in the channel estimator based on MA filter, it provides considerable performance gains against Rayleigh fading and reduces the optimum filter tap number. Consequently, the channel estimation delay time and the complexity of the receiver are reduced. In addition, the channel estimator based on IIR filter has the advantages such as little memory requirement and no delay time compared to the MA scheme. However, IIR filter coefficients is very sensitive to the mobile speed change and it exerts a serious influence upon the performance. For that reason, it is important to set uP the optimum IIR filter coefficients.