• ETRI Journal
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• v.46 no.5
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• pp.817-828
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• 2024

Owing to the widespread advancement of transformer-based artificial neural networks, artificial intelligence (AI) processors are now required to perform matrix-vector multiplication in addition to the conventional matrix-matrix multiplication. However, current AI processor architectures are optimized for general matrix-matrix multiplications (GEMMs), which causes significant throughput degradation when processing general matrix-vector multiplications (GEMVs). In this study, we proposed a port-folding GEMV (PF-GEMV) scheme employing multiformat and low-precision techniques while reusing an outer product-based processor optimized for conventional GEMM operations. This approach achieves 93.7% utilization in GEMV operations with an 8-bit format on an 8 × 8 processor, thus resulting in a 7.5 × increase in throughput compared with that of the original scheme. Furthermore, when applied to the matrix operation of the GPT-2 large model, an increase in speed by 7 × is achieved in single-batch inferences.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.12
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• pp.723-731
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• 2005

The $4{\times}4$ homogeneous transformation matrix is a compact representation of orientation and position of an object in robotics and computer graphics. A coordinate transformation is accomplished through the successive multiplications of homogeneous matrices, each of which represents the orientation and position of each corresponding link. Thus, for real time control applications in robotics or animation in computer graphics, the fast multiplication of homogeneous matrices is quite demanding. In this paper, a parallel-architecture vector processor is designed for this purpose. The processor has several key features. For the accuracy of computation for real application, the operands of the processors are floating point numbers based on the IEEE Standard 754. For the parallelism and reduction of hardware redundancy, the processor takes column vectors of homogeneous matrices as multiplication unit. To further improve the throughput, the processor structure and its control is based on a pipe-lined structure. Since the designed processor can be used as a special purpose coprocessor in robotics and computer graphics, additionally to special matrix/matrix or matrix/vector multiplication, several other useful instructions for various transformation algorithms are included for wide application of the new design. The suggested instruction set will serve as standard in future processor design for Robotics and Computer Graphics. The design is verified using FPGA implementation. Also a comparative performance improvement of the proposed design is studied compared to a uni-processor approach for possibilities of its real time application.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.2
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• pp.44-50
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• 1993

In this paper, we will present an array processor for implementation of digital neural networks. Back-propagation model can be formulated as a consecutive matrix-vector multiplication problem with some prespecified thresholding operation. This operation procedure is suited for the design of an array processor, because it can be recursively and repeatedly executed. Systolic array circuit architecture with Residue Number System is suggested to realize the efficient arithmetic circuit for matrix-vector multiplication and compute sigmoid function. The proposed design method would expect to adopt for the application field of neural networks, because it can be realized to currently developed VLSI technology.

• Journal of applied mathematics & informatics
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• v.7 no.2
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• pp.439-451
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• 2000

To compute derivatives using matrix vector multiplication method, new algorithms were introduced in [1.2]n By these algorithms, we reduced roundoff error in computing derivative using Chebyshev collocation methods (CCM). In this paper, some applications of these algorithms ar presented.

• Journal of Information Processing Systems
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• v.16 no.6
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• pp.1359-1371
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• 2020

In transmitting and receiving such a large amount of data, reliable data communication is crucial for normal operation of a device and to prevent abnormal operations caused by errors. Therefore, in this paper, it is assumed that an error correction code (ECC) that can detect and correct errors by itself is used in an environment where massive data is sequentially received. Because an embedded system has limited resources, such as a low-performance processor or a small memory, it requires efficient operation of applications. In this paper, we propose using an accelerated ECC-decoding technique with a graphics processing unit (GPU) built into the embedded system when receiving a large amount of data. In the matrix-vector multiplication that forms the Hamming code used as a function of the ECC operation, the matrix is expressed in compressed sparse row (CSR) format, and a sparse matrix-vector product is used. The multiplication operation is performed in the kernel of the GPU, and we also accelerate the Hamming code computation so that the ECC operation can be performed in parallel. The proposed technique is implemented with CUDA on a GPU-embedded target board, NVIDIA Jetson TX2, and compared with execution time of the CPU.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.9 no.3
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• pp.127-131
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• 1984

The IOVMM(Incoherent Optical Vector Matrix Multiplier) is constructed, which can process much information very fast by incogerent light source, and its experimental results are compared with the theoretical values. The input vector and matirx elements are limited to the positive number in this paper. The input vector is made by the LED array and the matrix is encoded on the film by the area modulation method. The result of the vector-matrix multiplication is detected by the photodiode array through the lens system. The analog multiplexer is used for looking at output signal on one channel.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.61-69
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• 2009

This paper presents the design results of a low complexity and high throughput LDPC encoder structure. In order to solve the high complexity problem of the LDPC encoder, a simplified matrix-vector multiplier is proposed instead of the conventional complex matrix-vector multiplier. The proposed encoder also adopts a partially parallel structure and performs column-wise operations in matrix-vector multiplication to achieve high throughput. Implementation results show that the proposed architecture reduces the number of logic gates and memory elements by 37.4% and 56.7%, compared with existing five-stage pipelined architecture. The proposed encoder also supports 800Mbps throughput at 40MHz clock frequency which is improved about three times more than the existing architecture.

• Journal of Information Technology Services
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• v.6 no.1
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• pp.151-158
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• 2007

D-class computation requires multiplication of three Boolean matrices for each of all possible triples of $n{\times}n$ Boolean matrices and search for equivalent $n{\times}n$ Boolean matrices according to a specific equivalence relation. It is easy to see that even multiplying all $n{\times}n$ Boolean matrices with themselves shows exponential time complexity and D-Class computation was left an unsolved problem due to its computational complexity. The vector-based multiplication theory shows that the multiplication of three Boolean matrices for each of all possible triples of $n{\times}n$ Boolean matrices can be done much more efficiently. However, D-Class computation requires computation of equivalent classes in addition to the efficient multiplication. The paper discusses a theory and an algorithm for efficient D-class computation, and shows execution results of the algorithm.

• Journal of the Korea Computer Graphics Society
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• v.16 no.4
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• pp.11-16
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• 2010

We present an efficient algorithm for rendering sweep surfaces using programmable graphics hardware. A sweep surface can be represented by a cross-section curve undergoing a spline motion. This representation has a simple matrix-vector multiplication structure that can easily be adapted to programmable graphics hardware. The data for the motion and cross-section curves are stored in texture memory. The vertex processor considers a pair of surface parameters as a vertex and evaluates its coordinates and normal vector with a single matrix multiplication. Using the GPU in this way is between 10 and 40 times as fast as CPU-based rendering.

• Journal of Ship and Ocean Technology
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• v.7 no.3
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• pp.56-65
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• 2003

The hull monitoring systems of container ships with four long-base gages give enough information for identifying the hull girder loads such as bending and torsional moments. But such a load-identification for container ships has not been known. In this paper, a load-identification method is suggested in terms of a linear matrix equation that the measured strain vector equals to the multiplication of the transformation matrix and the desired strain component vector. The equation is proved to be mathematically complete by the property of positive-definite determinant of the transformation matrix. The method is applied to a hull stress monitoring system for 8100TED container ship during sea trial, and the estimated external loads illustrate reasonable results in comparison with the pre-estimated results. This moment decomposition concept has also been tested in real operation conditions. The typical phenomena over the Suez Canal illustrated very suitable results comparing with the physical understandings. Henceforth, one can effectively use the proposed concept to monitor the hull girder loads such as bending and torsional moments.