• Title/Summary/Keyword: matching circuit

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Fuzzy Hardware Implementation using the Hausdorff Distance (Hausdorff Distance를 이용한 퍼지 하드웨어 구현)

  • 김종만;변오성;문성룡
    • Proceedings of the IEEK Conference
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    • 2000.06d
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    • pp.147-150
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    • 2000
  • Hausdorff distance(HD) commonly used measures for object matching, and calculates the distance between two point set of pixels in two-dimentional binary images without establishing correspondence. And it is realized as the image filter applying the fuzzy. In this paper, the fuzzy hardware realizes in order to construct the image filter applying HD, also, propose as the method for the noise removal using it in the image. MIN-MAX circuit designs the circuit using MAX-PLUS, and the fuzzy HD hardware results are obtained to the simulation. And then, the previous computer simulation is confirmed to the result by using MATLAB.

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Current-Mode Electronically Tunable Universal Filter Using Only Plus-Type Current Controlled Conveyors and Grounded Capacitors

  • Minaei, Shahram;Turkoz, Sait
    • ETRI Journal
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    • v.26 no.4
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    • pp.292-296
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    • 2004
  • In this paper we present a new current-mode electronically tunable universal filter using only plus-type current controlled conveyors (CCCII+s) and grounded capacitors. The proposed circuit can simultaneously realize lowpass, bandpass, and highpass filter functions - all at high impedance outputs. The realization of a notch response does not require additional active elements. The circuit enjoys an independent current control of parameters $\omega_0$ and $\omega_0/Q$. No element matching conditions are imposed. Both its active and passive sensitivities are low.

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Monolithic X-band Mixer (모노리식 X-band 혼합기)

  • Jun, Yong-Il;Park, Hyung-Moo;Ma, Dong-Sung
    • Proceedings of the KIEE Conference
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    • 1988.07a
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    • pp.426-429
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    • 1988
  • A simple design method of a single balanced MMIC mixer is described. It uses small signal S11 and capacitive load for the input matching circuit and the output loading circuit, respectively. It is found that the conversion gain of the FET mixer is independent of FET gate width. The fabricated mixer has 2.5 dB conversion gain at 9 GHz with 50 ohm IF load and 2 dBm local oscillator power.

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A Low Distortion and Low Dissipation Power Amplifier with Gate Bias Control Circuit for Digital/Analog Dual-Mode Cellular Phones

  • Maeng, Sung-Jae;Lee, Chang-Seok;Youn, Kwang-Jun;Kim, Hae-Cheon;Mun, Jae-Kyung;Lee, Jae-Jin;Pyun, Kwang-Eui
    • ETRI Journal
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    • v.19 no.2
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    • pp.35-47
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    • 1997
  • A power amplifier operating at 3.3 V has been developed for CDMA/AMPS dual-mode cellular phones. It consists of linear GaAs power MESFET's, a new gate bias control circuit, and an output matching circuit which prevents the drain terminal of the second MESF from generating the harmonics. The relationship between the intermodulation distortion and the spectral regrowth of the power amplifier has been investigated with gate bias by using the two-tone test method and the adjacent channel leakage power ratio (ACPR) method of CDMA signals. The dissipation power of the power amplifier with a gate bias control circuit is minimized to below 1000 mW in the range of the low power levels while satisfying the ACPR of less than -26 dBc for CDMA mode. The ACPR of the power amplifier is measured to be -33 dBc at a high output power of 26 dBm.

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Analog CMOS Performance Degradation due to Edge Direct Tunneling (EDT) Current in sub-l00nm Technology

  • Navakanta Bhat;Thakur, Chandrabhan-Singh
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.3 no.3
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    • pp.139-144
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    • 2003
  • We report the results of extensive mixed mode simulations and theoretical analysis to quantify the contribution of the edge direct tunneling (EDT) current on the total gate leakage current of 80nm NMOSFET with SiO2 gate dielectric. It is shown that EDT has a profound impact on basic analog circuit building blocks such as sample-hold (S/H) circuit and the current mirror circuit. A transistor design methodology with zero gate-source/drain overlap is proposed to mitigate the EDT effect. This results in lower voltage droop in S/H application and better current matching in current mirror application. It is demonstrated that decreasing the overlap length also improves the basic analog circuit performance metrics of the transistor. The transistor with zero gate-source/drain overlap, results in better transconductance, input resistance, output resistance, intrinsic gain and unity gain transition frequency.

Impedance Tuning and Matching Characteristics of UHF RFID Tag for Increased Reading Range (인식거리 향상을 위한 UHF 대역 RFID 태그 임피던스 정합 설계)

  • Lee, Jong-Wook;Kwon, Hong-Il;Lee, Bom-Son
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
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    • 2005.11a
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    • pp.279-284
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    • 2005
  • We investigated the impedance matching characteristics of UHF-band RFID tag antenna and tag chip for increased reading range. A voltage multiplier designed using 0.4 $\mu$m zero-$V_T$ MOSFET showed that DC output voltage of about 2 V can be obtained using standard CMOS process. The input impedance of the voltage multiplier was examined to achieve impedance matching to the RFID tag antenna using analytical and numerical approaches. The input impedance of the voltage multiplier could be varied in a wide range by selecting the size of MOSFET and the number of multiplying stages, and thus can be impedance matched to a tag antenna in presence of other tag circuit blocks. A meander line inductively-coupled RFID tag antenna operating at UHF band also shows the feasibility of impedance matching to tile RFID tag chip.

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Analysis of Stepped T-Junction using Improved Three Plane Mode Matching Method and Its Application (개선된 Three Plane Mode Matching Method를 이용한 계단형 T-접합의 해석과 응용)

  • 손영일;김상태;황충선;백락준;신철재
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.6B
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    • pp.1123-1133
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    • 1999
  • In this paper, we applied mode matching and generalized scattering matrix methods to three plane mode matching method for analyzing T-junctions. We calculated all scattering matrix elements by only three times and considered several incident modes. By proposed analysis method, we could analyze various waveguide discontinuity structures more conveniently and accurately. Using the stepped T-junction, we would be able to reduce the reflection coefficient at an input port and use it over wider band. Simulated and HFSS data of T-junctions are compared, showing good agreement for scattering matrix elements. Considering step numbers, height, length and position, we extracted for optimum dimensions and equivalent circuit parameters.

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Application of the Inverse Scattering Theory to the Design of the Tapered Impedance-Matching Line (테이퍼형 임피던스 정합선로의 설계를 위한 역산란 이론의 응용)

  • 송충호;이상설
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.12 no.7
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    • pp.1139-1146
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    • 2001
  • A tapered impedance-matching line is designed by an inverse scattering method for the one-dimensional medium. The phase compensation factor(PCF) is introduced in order to reduce the error in the inverse scattering process to reconstruct the permittivity profile. By estimating the permittivity profile of the virtual one-dimensional dielectric medium whose reflection characteristic is the same as that of the specified matching line, the matching line is synthesized. The method can be used to design impedance-matching lines with arbitrary passband characteristics without any equivalent circuit analysis. The inevitable errors in the method using the time-domain reflection coefficient can be avoided by using the frequency-domain reflection coefficient.

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C-Band Internally Matched GaAs Power Amplifier with Minimized Memory Effect (Memory Effect를 최소화한 C-대역 내부 정합 GaAs 전력증폭기)

  • Choi, Woon-Sung;Lee, Kyung-Hak;Eo, Yun-Seong
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.24 no.11
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    • pp.1081-1090
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    • 2013
  • In this paper, a C-band 10 W power amplifier with internally matched input and output matching circuit is designed and fabricated. The used power transistor for the power amplifier is GaAs pHEMT bare-chip. The wire bonding analysis considering the size of the capacitor and the position of transistor pad improves the accurate design. The matching circuit design with the package effect using EM simulation is performed. To reduce the unsymmetry of IMD3 in 2-tone measurement due to the memory effect, the bias circuit minimizing the memory effect is proposed and employed. The measured $P_{1dB}$, power gain, and power added efficiency are 39.8~40.4 dBm, 9.7~10.4 dB, and 33.4~38.0 %, respectively. Adopting the proposed bias circuit, the difference between the upper and lower IMD3 is less than 0.76 dB.

Method of PCB Short Circuit Detection using SURF (SURF를 이용한 PCB 쇼트-서킷 검출 방법)

  • Hwang, Dae-Dong;Shin, Si-Woo;Lee, Keun-Soo
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.11
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    • pp.5471-5478
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    • 2012
  • In this paper, we propose a new short-circuit detecting method which can detect bad short-circuits, one of bad types occurring in PCB(Printed Circuit Board), by using SURF(Speeded-Up Robust Features) algorithm. The basic procedure in the proposed method sequentially consists of extracting features from both sample and inputted images by SURF, performing perspective transform by feature matching and matching results, extracting check areas of interest, binary coding and extracting short-circuits, and verifying results. The proposed method focuses on the robustness which can detect bad short-circuits even though the position and angle of PCB are not uniform and arbitrarily placed. Experimental results show that our method enables to detect bad short-circuits regardless of the location and angle of PCB placed variously and validate that the proposed method outperforms the conventional methods detecting bad short-circuits manually on the aspect of both the detection rate and time.