• Journal of KIISE:Computer Systems and Theory
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• v.37 no.4
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• pp.215-225
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• 2010

The NAND flash memory based SSDs are considered to replace the existing HDDs. To maximize the I/O performance, SSD is composed of several NAND flash memories in parallel. However, to adopt the hybrid mapping scheme in SSD may cause degradation of the I/O performance. In this paper, we propose a new mapping scheme for the SSD called WADPM. WADPM loads only necessary mapping information into RAM and dynamically adjusts the size of mapping information in the RAM. So, WADPM avoids the shortcoming of page-level mapping scheme that requires too large mapping table. Performance evaluation using simulations shows that I/O performance of WADPM is 3.5 times better than the hybrid-mapping scheme and maximum size of mapping table of WADPM is about 50% in comparison with the page-level mapping scheme.

• Journal of the Korea Society of Computer and Information
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• v.26 no.2
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• pp.11-18
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• 2021

The flash translation layer(FTL) of SSD maps the logical page number requested from the host to the actual recorded flash memory page number. It is very important to reduce the amount of RAM used to manage the mapping information. In the existing demand-based FTLs, two-level method is applied in which mapping information is also recorded in flash memory pages and only their addresses are managed as a table in RAM. As the capacities of SSDs are growing to tens of terabytes, the amount of RAM for mapping table becomes too large. In this paper, ML-FTL was proposed as a method of managing mapping information in three levels to reduce the amount of RAM required drastically. From an evaluation, the increase in overhead was minimal compared to the conventional two-level method by properly utilizing cache.

• Journal of Broadcast Engineering
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• v.15 no.6
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• pp.757-767
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• 2010

In this paper, we have studied the color compensation method for 3D that enables 3D color presentation similar to 2D. The color compensation method uses the difference of color presentation in 2D and 3D mode. First, the RGB I/O relationship curve was derived in 2D and 3D mode based on the input RGB color bar images. The relationship was modeled in modified power-law forms. Based on the modeling information, we generated color mapping tables, which can be used for compensating the difference of colors. The proposed color mapping block can be added at the output block of a 3DTV system, where the 2D content can be bypassed but the 3D content RGB data can be processed using the color mapping table. The experimental results show that the proposed method improves color presentation of a 3DTV system using a proper color compensation based on 2D presentation.

• Journal of Digital Contents Society
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• v.10 no.4
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• pp.633-637
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• 2009

In this paper, we present the reuse module library generating algorithm and register-transfer (RT) library generating algorithm considering the power consumption of reuse module for field-programmable gate array (FPGA) technology mapping in order to implement into the circuit for calculating power consumption. To realize the circuit of calculation of power consumption, the FPGA is selected. Considering lookup table (LUT) conditions of selected FPGA, technology mapping process is conducted to minimize the total power consumption. With these information, the circuit is realized using suitable given power consumption among allocated results of modules.

• Proceedings of the IEEK Conference
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• summer
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• pp.122-127
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• 2004

The color gamut mapping method that is used for enhancing the color reproduction quality between PC monitor and printer devices is adopted for display quality enhancement. The high definition display devices operate at the clock speed of around $70\;MHz\;\sim\;150\;MHz$ and permit several nano seconds for real-time processing. Thus, the concept of three-dimensional reduced resolution look-up table is used. The required hardware can be greatly reduced by look-up table resolution adjustment. The proposed hardware architecture is successfully implemented in ASIC and also successfully adopted in display quality enhancement purposes.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.693-694
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• 2006

The high definition digital TV display devices need real-time gamut mapping. This paper proposes a gamut mapping algorithm that used three dimensional reduced resolution look up table and tetrahedral interpolation for real-time processing. The proposed hardware architecture is successfully implemented in FPGA and ASIC.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.15-18
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• 2003

Flash memory becomes more important for its fast access speed, low-power, shock resistance and nonvolatile storage. But its native restrictions that have limited 1ifetime, inability of update in place, different size unit of read/write and erase operations need to managed by FTL(Flash Translation Layer). FTL has to control the wear-leveling, address mapping, bad block management of flash memory. In this paper, we focuses on the fast access to address mapping table and proposed the way of faster valid page search in the flash memory using the VPLT(Valid Page Lookup Table). This method is expected to decrease the frequency of access of flash memory that have an significant effect on performance of read and block-transfer operations. For the validations, we implemented the FTL based on Windows CE platform and obtained an improved result.

• Journal of the Korea Society of Computer and Information
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• v.15 no.8
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• pp.23-30
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• 2010

Flash memory is non-volatile and can retain data even after system is powered off. Besides, it has many other features such as fast access speed, low power consumption, attractive shock resistance, small size, and light-weight. As its price decreases and capacity increases, the flash memory is expected to be widely used in consumer electronics, embedded systems, and mobile devices. Flash storage systems generally adopt a software layer, called FTL. In this research, we proposed a new FTL mechanism for overcoming the major drawback of conventional block mapping algorithm. In addition to the block mapping table, a index block mapping table with a small size is used to indicate sector location. The proposed indexed block mapping algorithm by adding a small size. By the simulation result, the proposed FTL provides an enhanced speed than a conventional hybrid mapping algorithm by around 45% in average, and the requirement of mapping memory is also reduced by around 12%.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.04a
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• pp.506-507
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• 2015

Our scheme going to use the advanteges of shadow technical and use it in flash memory. With our scheme we can maintain the system from corruption by making a capy table for table mappinng. It is make us to recover the data easily when something unusually happen to the system.

• Journal of Korea Multimedia Society
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• v.16 no.3
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• pp.318-329
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• 2013

This paper proposes a DNA watermarking method for the privacy protection and the prevention of illegal copy. The proposed method allocates codons to random circular angles by using random mapping table and selects triplet codons for embedding target with the help of the Lipschitz regularity value of local modulus maxima of codon circular angles. Then the watermark is embedded into circular angles of triplet codons without changing the codes of amino acids in a DNA. The length and location of target triplet codons depend on the random mapping table for 64 codons that includes start and stop codons. This table is used as the watermark key and can be applied on any codon sequence regardless of the length of sequence. If this table is unknown, it is very difficult to detect the length and location of them for extracting the watermark. We evaluated our method and DNA-crypt watermarking of Heider method on the condition of similar capacity. From evaluation results, we verified that our method has lower base changing rate than DNA-crypt and has lower bit error rate on point mutation and insertions/deletions than DNA-crypt. Furthermore, we verified that the entropy of random mapping table and the locaton of triplet codons is high, meaning that the watermark security has high level.