• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.765-770
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• 2012

In this paper, we proposed an effective hardware structure using DCT-based inra-prediction mode selection to reduce computational complexity caused by intra mode decision. In this hardware structure, the input block is transformed at first and then analyzed to determine its texture directional tendency. the complexity has solved by performing intra prediction in only predicted edge direction. $4{\times}4$ DCT is calculated in one cycle using Multitransform_PE and Inta_pred_PE calculates one prediction mode in two cycles. Experimental results show that the proposed Intra prediction encoding needs only 517 cycles for one macroblock encoding. This architecture improves the performance by about 17% than previous designs. For hardware implementation, the proposed intra prediction encoder is implemented using Verilog HDL and synthesized with Megnachip $0.18{\mu}m$ standard cell library. The synthesis results show that the proposed architecture can run at 125MHz.