• Journal of Plant Biotechnology
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• v.47 no.2
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• pp.157-163
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• 2020

Calmodulin (CaM) mediates cellular Ca²⁺ signals in the defense responses of plants. We previously reported that GmCaM-4 and 5 are involved in salicylic acid-independent activation of disease resistance responses in soybean (Glycine max). Here, we generated a GmCaM-4 cDNA construct under the control of the cauliflower mosaic virus (CaMV) 35S promoter and transformed this construct into potato (Solanum tuberosum L.). The constitutive over-expression of GmCaM-4 in potato induced high-level expression of pathogenesis-related (PR) genes, such as PR-2, PR-3, PR-5, phenylalanine ammonia-lyase (PAL), and proteinase inhibitorII (pinII). In addition, the transgenic potato plants exhibited enhanced resistance against a bacterial pathogen, Erwinia carotovora ssp. Carotovora (ECC), that causes soft rot disease and showed spontaneous lesion phenotypes on their leaves. These results strongly suggest that a CaM protein in soybean, GmCaM-4, plays an important role in the response of potato plants to pathogen defense signaling.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.11C
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• pp.1120-1127
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• 2006

[ $GF(2^m)$ ] for elliptic curve cryptosystem. The proposed multiplier uses Gaussian normal basis representation and produces multiplication results at a rate of one per [m/w] clock cycles, where w is the selected we.4 size. We implement the p.oposed design using Xilinx XC2V1000 FPGA device. Our design has significantly less critical path delay compared with previously proposed hard ware implementations.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.3
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• pp.93-100
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• 2007

Since Koblitz and Miller suggested the use of elliptic curves in cryptography, there has been an extensive literature on elliptic curve cryptosystem (ECC). The use of ECC is based on the observation that the points on an elliptic curve form an additive group under point addition operation. To realize secure cryptosystems using these groups, it is very important to find an elliptic curve whose group order is divisible by a large prime, and also to find a base point whose order equals this prime. While there have been many dramatic improvements on finding an elliptic curve and computing its group order efficiently, there are not many results on finding an adequate base point for a given curve. In this paper, we propose an efficient method to find a random base point on an elliptic curve defined over $GF(p^m)$. We first show that the critical operation in finding a base point is exponentiation. Then we present efficient algorithms to accelerate exponentiation in $GF(p^m)$. Finally, we implement our algorithms and give experimental results on various practical elliptic curves, which show that the new algorithms make the process of searching for a base point 1.62-6.55 times faster, compared to the searching algorithm based on the binary exponentiation.

• Journal of Plant Biotechnology
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• v.38 no.1
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• pp.62-68
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• 2011

Calmodulin (CaM), a $Ca^{2+}$ binding protein in eukaryotes, mediates cellular $Ca^{2+}$ signals in response to a variety of biotic and abiotic external stimuli. The $Ca^{2+}$-bound CaM transduces signals by modulating the activities of numerous CaM-binding proteins. As a CaM binding protein, AtCBP63 ($\b{A}$rabidopsis thaliana $\b{C}$aM-binding protein $\underline{63}$ kD) has been known to be positively involved in plant defense signaling pathway. To investigate the pathogen resistance function of AtCBP63 in potato, we constructed transgenic potato (Solanum tuberosum L.) plants constitutively overexpressing AtCBP63 under the control of cauliflower mosaic virus (CaMV) 35S promoter. The overexpression of the AtCBP63 in potato plants resulted in the high level induction of pathogenesis-related (PR) genes such as PR-2, PR-3 and PR-5. In addition, the AtCBP63 transgenic potato showed significantly enhanced resistance against a pathogen causing bacterial soft rot, Erwinia carotovora ssp. Carotovora (ECC). These results suggest that a CaM binding protein from Arabidopsis, AtCBP63, plays a positive role in pathogen resistance in potato.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.3
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• pp.197-203
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• 2009

Finite field arithmetic is very important in the area of cryptographic applications and coding theory, and it is efficient to use normal bases in hardware implementation. Using the fact that $GF(2^{mk})$ having a type-I optimal normal basis becomes the extension field of $GF(2^m)$, we, in this paper, propose a new serial multiplier which reduce the critical XOR path delay of the best known Reyhani-Masoleh and Hasan's serial multiplier by 25% and the number of XOR gates of Kwon et al.'s multiplier by 2 based on the Reyhani-Masoleh and Hasan's serial multiplier for type-I optimal normal basis.

• Proceedings of the KIEE Conference
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• 2006.11a
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• pp.158-160
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• 2006

The role of SVL (Sheath voltage limiter) in cable system is to protect the PVC(or PE) jacket in case of transient overvoltage resulting from lightning and other causes. But, in Korea, there is so many SVL failure cases resulting from power frequency overvoltage. So, the paper investigates the phenomenon of failure SVL comparing with other countries' system. Finally, the installation of ECC(Earth Connectivity Conductor) in under ground cable system is presented to remove the possibilities of SVL thermal runaway due to the power frequency overvoltage.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.1515-1518
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• 2009

최적정규기저(Optimal Normal Basis)를 이용한 $GF(2^m)$상의 곱셈은 ECC(Elliptic Curve Cryptosystems: 타원곡선 암호시스템) 및 유한체 산술 연산의 하드웨어 구현에 적합하다는 것은 잘 알려져 있다. 본 논문에서는 최적정규기저의 하드웨어적 장점을 이용하여 합성체(Composit Field)상의 곱셈기를 제안하며, 기존에 제안된 합성체상의 곱셈기와 비교 및 분석한다. 제안된 곱셈기는 최적정규기저 타입 I, II의 대칭성과 가수의 중복성을 이용한 열벡터의 재배열에 따른 XOR 연산의 재사용으로 낮은 하드웨어 복잡도와 작은 지연시간을 가진다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.5
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• pp.2680-2700
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• 2017

Finite field arithmetic over GF($2^m$) is used in a variety of applications such as cryptography, coding theory, computer algebra. It is mainly used in various cryptographic algorithms such as the Elliptic Curve Cryptography (ECC), Advanced Encryption Standard (AES), Twofish etc. The multiplication in a finite field is considered as highly complex and resource consuming operation in such applications. Many algorithms and architectures are proposed in the literature to obtain efficient multiplication operation in both hardware and software. In this paper, a modified serial multiplication algorithm with interleaved modular reduction is proposed, which allows for an efficient realization of a sequential polynomial basis multiplier. The proposed sequential multiplier supports multiplication of any two arbitrary finite field elements over GF($2^m$) for generic irreducible polynomials, therefore made versatile. Estimation of area and time complexities of the proposed sequential multiplier is performed and comparison with existing sequential multipliers is presented. The proposed sequential multiplier achieves 50% reduction in area-delay product over the best of existing sequential multipliers for m = 163, indicating an efficient design in terms of both area and delay. The Application Specific Integrated Circuit (ASIC) and the Field Programmable Gate Array (FPGA) implementation results indicate a significantly less power-delay and area-delay products of the proposed sequential multiplier over existing multipliers.

• ETRI Journal
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• v.25 no.6
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• pp.510-516
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• 2003

In this paper, we describe the development of a platform-based SoC of a 32-bit smart card. The smart card uses a 32-bit microprocessor for high performance and two cryptographic processors for high security. It supports both contact and contactless interfaces, which comply with ISO/IEC 7816 and 14496 Type B. It has a Java Card OS to support multiple applications. We modeled smart card readers with a foreign language interface for efficient verification of the smart card SoC. The SoC was implemented using 0.25 ${\mu}m$ technology. To reduce the power consumption of the smart card SoC, we applied power optimization techniques, including clock gating. Experimental results show that the power consumption of the RSA and ECC cryptographic processors can be reduced by 32% and 62%, respectively, without increasing the area.

• Review of KIISC
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• v.16 no.3
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• pp.25-33
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• 2006

본 논문에서는 임베디드 시스템 온칩 적용을 위한 통합 보안 프로세서를 SIP(Semiconductor Intellectual Property)로 설계하였다. 각각의 SIP는 VHDL RTL로 모델링하였으며, 논리합성, 시뮬레이션, FPGA 검증을 통해 재사용이 가능하도록 구현하였다. 또한 ARM9과 SIP들이 서로 통신이 가능하도록 AMBA AHB의 스펙에 따라 버스동작모델을 설계, 검증하였다. 플랫폼기반의 통합 보안 SIP는 ECC, AES, MD-5가 내부 코어를 이루고 있으며 각각의 SIP들은 ARM9과 100만 게이트 FPGA가 내장된 디바이스를 사용하여 검증하였으며 최종적으로 매그나칩 $0.25{\mu}m(4.7mm\times4.7mm)$ CMOS 공정을 사용하여 MPW(Multi-Project Wafer) 칩으로 제작하였다.