• Journal of information and communication convergence engineering
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• 제12권4호
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• pp.252-256
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• 2014

Traditional block cipher Advanced Encryption Standard (AES) is widely used in the field of network security, but it has high overhead on each operation. In the 15th international workshop on information security applications, a novel lightweight and low-power encryption algorithm named low-power encryption algorithm (LEA) was released. This algorithm has certain useful features for hardware and software implementations, that is, simple addition, rotation, exclusive-or (ARX) operations, non-Substitute-BOX architecture, and 32-bit word size. In this study, we further improve the LEA encryptions for cloud computing. The Web-based implementations include JavaScript and assembly codes. Unlike normal implementation, JavaScript does not support unsigned integer and rotation operations; therefore, we present several techniques for resolving this issue. Furthermore, the proposed method yields a speed-optimized result and shows high performance enhancements. Each implementation is tested using various Web browsers, such as Google Chrome, Internet Explorer, and Mozilla Firefox, and on various devices including personal computers and mobile devices. These results extend the use of LEA encryption to any circumstance.

• 전기전자학회논문지
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• 제22권3호
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• pp.846-849
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• 2018

Wireless power transfer (WPT) is the technology that enables the power to transmit electromagnetic field to an electrical load without the use of wires. There are two kinds of magnetic resonant coupling and inductive coupling ways transmitting from the source to the output load. Compared with microwave method for energy transfer over a long distance, the magnetic resonance method has the advantages of reducing the barrier of electromagnetic wave and enhancing the efficiency of power transmission. In this paper, the wireless power transfer circuit having a resonant frequency of 13.45 MHz for the low power system is studied, and the hardware implementation is accomplished to measure the power transmission efficiency for the distance between the transmitter and the receiver.

• ETRI Journal
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• 제39권3호
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• pp.326-335
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• 2017

In the uplink transmission of massive (or large-scale) multi-input multi-output (MIMO) systems, large dimensional signal detection and its hardware design are challenging issues owing to the high computational complexity. In this paper, we propose low-complexity hardware architectures of Richardson iterative method-based massive MIMO detectors. We present two types of massive MIMO detectors, directly mapped (type1) and reformulated (type2) Richardson iterative methods. In the proposed Richardson method (type2), the matrix-by-matrix multiplications are reformulated to matrix-vector multiplications, thus reducing the computational complexity from $O(U^2)$ to O(U). Both massive MIMO detectors are implemented using a 65 nm CMOS process and compared in terms of detection performance under different channel conditions (high-mobility and flat fading channels). The hardware implementation results confirm that the proposed type1 Richardson method-based detector demonstrates up to 50% power savings over the proposed type2 detector under a flat fading channel. The type2 detector indicates a 37% power savings compared to the type1 under a high-mobility channel.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 신호처리소사이어티 추계학술대회 논문집
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• pp.83-86
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• 2003

In this paper, we propose a new hardware architecture for integer transform, quantizer operation of a new video coding standard H.264/JVT. We describe the algorithm to derive hardware architecture emphasizing the importance of area for low cost and low power consumption. The proposed architecture has been verified by PCI-interfaced emulation board using APEX-II Altera FPGA and also by ASIC synthesis using Samsung 0.18 ${\mu}{\textrm}{m}$ CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 100 MHz, processing more than 1, 300 QCIF video frames per second. The hardware is going to be used as a core module when implementing a complete H.264 video encoder/decoder ASIC for real-time multimedia application.

• 전기전자학회논문지
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• 제24권3호
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• pp.895-900
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• 2020

본 논문에서 BSPE는 전력이 많이 소모되는 기존의 곱셈 알고리즘을 대체했다. Bit-serial Multiplier를 이용해 하드웨어 자원을 줄였으며, 메모리 사용량을 줄이기 위해 가변적인 정수 형태의 데이터를 사용한다. 또한, 부분 합을 더하는 MOA(Multi Operand Adder)에 LOA(Lower-part OR Approximation)를 적용해서 MOA의 자원 사용량 및 전력사용량을 줄였다. 따라서 기존 MBS(Multiplication by Barrel Shifter)보다 하드웨어 자원과 전력이 각각 44%와 42%가 감소했다. 또한, BSPE Core를 위한 hardware architecture design을 제안한다.

• International Journal of Advanced Culture Technology
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• 제7권4호
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• pp.313-320
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• 2019

Nowadays, as the availability of tiny, low-cost microcomputer increases at a high level, mobile robots are experiencing remarkable enhancements in hardware design, software performance, and connectivity advancements. In order to control Turtlebot 2, several algorithms have been developed using the Robot Operating System(ROS). However, ROS requires to be run on a high-cost computer which increases the hardware cost and the power consumption to the robot. Therefore, design an algorithm based on low-cost hardware is the most innovative way to reduce the unnecessary costs of the hardware, to increase the performance, and to decrease the power consumed by the computer on the robot. In this paper, we present a path-finding algorithm for TurtleBot 2 based on low-cost hardware. We implemented the algorithm using Raspberry pi, Windows 10 IoT core, and RPLIDAR A2. Firstly, we used Raspberry pi as the alternative to the computer employed to handle ROS and to control the robot. Raspberry pi has the advantages of reducing the hardware cost and the energy consumed by the computer on the robot. Secondly, using RPLIDAR A2 and Windows 10 IoT core which is running on Raspberry pi, we implemented the path-finding algorithm which allows TurtleBot 2 to navigate from the starting point to the destination using the map of the area. In addition, we used C# and Universal Windows Platform to implement the proposed algorithm.

• 한국정보전자통신기술학회논문지
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• 제10권2호
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• pp.141-146
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• 2017

본 논문에서는 저전력 영상 특징 추출 하드웨어 설계를 위한 하드웨어 폴딩 기법 기반 저면적 Gradient magnitude 연산기 구조를 제안한다. 하드웨어 복잡도를 줄이기 위해 Gradient magnitude 벡터의 특징을 분석하여 기존 알고리즘을 하드웨어를 공유하여 사용할 수 있는 알고리즘으로 변경하여 Folding 구조가 적용될 수 있도록 했다. 제안된 하드웨어 구조는 기존 알고리즘의 특징을 최대한 이용했기 때문에 데이터 품질의 열화가 거의 없이 구현될 수 있다. 제안된 하드웨어 구조는 Altera Quartus II v16.0 환경에서 Altera Cyclone VI (EP4CE115F29C7N) FPGA를 이용하여 구현되었다. 구현 결과, 기존 하드웨어 구조를 이용하여 구현한 연산기와의 비교에서 41%의 logic elements, 62%의 embedded multiplier 절감 효과가 있음을 확인했다.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2005년도 종합학술발표회 논문집 Vol.15 No.1
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• pp.131-136
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• 2005

UWB is the most spotlighted wireless technology that transmits data at very high rates using low power over a wide spectrum of frequency band. UWB technology makes it possible to transmit data at rate over 100Mbps within 10 meters. To preserve important header information, MB-OFDM UWB adopts Reed-Solomon(23,17) code. In receiver, RS decoder needs high speed and low latency using efficient hardware. In this paper, we suggest the architecture of RS decoder for MB-OFDM UWB. We adopts Modified-Euclidean algorithm for key equation solver block which is most complex in area. We suggest pipelined processing cell for this block and show the detailed architecture of syndrome, Chien search and Forney algorithm block. At last, we show the hardware implementation results of RS decoder for ASIC implementation.

• 한국정보기술응용학회:학술대회논문집
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• 한국정보기술응용학회 2005년도 6th 2005 International Conference on Computers, Communications and System
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• pp.195-198
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• 2005

UWB is the most spotlighted wireless technology that transmits data at very high rates using low power over a wide spectrum of frequency band. UWB technology makes it possible to transmit data at rate over 100Mbps within 10 meters. To preserve important header information, MBOFDM UWB adopts Reed-Solomon(23,17) code. In receiver, RS decoder needs high speed and low latency using efficient hardware. In this paper, we suggest the architecture of RS decoder for MBOFDM UWB. We adopts Modified-Euclidean algorithm for key equation solver block which is most complex in area. We suggest pipelined processing cell for this block and show the detailed architecture of syndrome, Chien search and Forney algorithm block. At last, we show the hardware implementation results of RS decoder for ASIC implementation.

• 대한전자공학회논문지SD
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• 제47권6호
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• pp.22-34
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• 2010

기존의 영상 스케일러(scaler)들은 연산량과 하드웨어 복잡도를 줄이기 위해 선형 보간과 같은 간단한 보간을 적용함으로써 화질을 희생시키거나, 고품질 영상을 얻기 위하여 복잡한 보간 기법을 적용함으로써 전력소모와 크기가 큰 하드웨어 구조를 적용하여 왔다. 그러나 영상기기들의 소형화와 고화질 영상에 대한 사용자들의 욕구 증대로 소형, 저전력이면서 결과 영상의 화질 또한 우수한 스케일러의 개발이 중요시되고 있다. 따라서 본 논문은 실시간, 고화질, 소형, 저전력의 목표를 모두 달성할 수 있는 래스터 스캔(raster scan) 방식의 스케일러 하드웨어 구조를 제안한다. 본 논문에서 제안하는 스케일러는 기존의 3차 보간(cubic interpolation) 기법과 룩업테이블(look-up table) 구조를 개선하여 저전력화와 소형화를 달성하였다. 제안하는 스케일러 구조의 특징은 기존의 실시간 스케일러가 포함하던 버퍼를 라인메모리로 대체하여 메모리 접근 횟수를 줄임으로써 저전력을 달성할 수 있도록 했다는 것이며, 또한 기존의 룩업테이블 구조에서 사용하던 3차 보간 수식을 재정리하여 곱셈기 수와 룩업테이블의 크기를 줄임으로써 하드웨어를 소형화하는 방법을 제안하였다. 마지막으로 사용되는 계수의 크기에 따른 결과를 분석하여 영상의 화질과 하드웨어 크기 간의 최적의 타협점을 제시하였다.