• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.257-260
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• 2000

In this paper, a Gm-C filter for low voltage and low power applications using a fully-differential transconductor is presented. The designed transconductor using the series composite transistors and the low voltage composite transistors has wide input range at low supply voltage. A negative resistor load (NRL) technology for high DC gain of the transconductor is employed with a common mode feedback (CMFB). As a design example, the third-order Elliptic lowpass filter is designed. The designed filter is simulated and examined by HSPICE using 0.25${\mu}{\textrm}{m}$ CMOS n-well parameters. The simulation results show 105MHz cutoff frequency and 2.4㎽ power dissipation with a 2.5V supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1343-1348
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• 2011

A modified capacitive detection circuit of charge sharing scheme is proposed, which reduces the static power dissipation and increases the voltage difference between a ridge and valley more than a conventional circuit. The detection circuit is designed and simulated in 3.3V, $0.35{\mu}m$ standard CMOS process, 40MHz condition. The result shows about 47% power dissipation reduction and 90% improvement of difference between a ridge and valley sensing voltage. The proposed circuit is layout without area increasing of a one pixel.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.83-90
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• 2004

This paper proposes an efficient scan testing method for compression of test input data and reduction of test power for SOC. The proposed method determines whether some parts of a test response can be reused as a part of next input test data on the analysis of deterministic test data and its response. Our experimental results show that benchmark circuits have a high similarity between un-compacted deterministic input test data and its response. The proposed testing method achieves the average of 29.4% reduction of power dissipation based on the number of test clock and 69.7% reduction of test data for ISCAS'89 benchmark circuits.

• Journal of Electrical Engineering and Technology
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• v.7 no.4
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• pp.589-595
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• 2012

When surges and electromagnetic pulses from lightning or power conversion devices are considered, it is desirable to evaluate grounding system performance as grounding impedance. In the case of large-sized grounding electrodes or long counterpoises, the grounding impedance is increased with increasing the frequency of injected current. The grounding impedance is increased by the inductance of grounding electrodes. This paper presents the measured results of frequency-dependent grounding impedance and impedance phase as a function of the length of counterpoises. In order to analyze the frequency-dependent grounding impedance of the counterpoises, the frequency-dependent current dissipation rates were measured and simulated by the distributed parameter circuit model reflecting the frequency-dependent relative resistivity and permittivity of soil. As a result, the ground current dissipation rate is proportional to the soil resistivity near the counterpoises in a low frequency. On the other hand, the ground current dissipation near the injection point is increased as the frequency of injected current increases. Since the high frequency ground current cannot reach the far end of long counterpoise, the grounding impedance of long counterpoise approaches that of the short one in the high frequency. The results obtained from this work could be applied in design of grounding systems.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.104-110
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• 2011

A CMOS Image Sensor (CIS) mounted on mobile appliances requires low power consumption due to limitations of the battery life cycle. In order to reduce the power consumption of CIS, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination and a low power single slope analog-to-digital (A/D) converter with a sleep-mode comparator. Based on 0.13 ${\mu}m$ CMOS process, the chip satisfies QVGA resolution (320 ${\times}$ 240 pixels) that the cell pitch is 2.25 um and the structure is a 4-Tr active pixel sensor. From the experimental results, the performance of the CIS has a 10-b resolution, the operating speed of the CIS is 16 frame/s, and the power dissipation is 25 mW at a 3.3 V(analog)/1.8 V(digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption was reduced by approximately 22% in the sleep mode, and 20% in the active mode.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1221-1229
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• 1996

This paper proposes a heuristic algorithm for low power implementation of combinational circuits. Selecting an input variable for a given function, the proposed algorithm performs Shannon exansion with respect to the variable to reduce the number of gates in the subcircuit realizing the coffactor function, reducting the power dissipation of the implemented circuit. experimental results for the MCNC benchmarks show that the proposed algorithm is effective by generating the circuits consuming the power 48.9% less on the average, when compared to the previous algorithm based on precomputation logic.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1288-1291
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• 2002

In this paper, we present a design of mpeg-4 video codec chip to reduce the power consumption using frame level clock gating and motion estimation skip scheme. It performs 30 grames/s of codec (encoding and decoding) mode with quarter-common intermediate format(QCIF) at 27MHz. A novel low-power techniques were implemented in architectural level, which is 35% of the power dissipation for a conventional CMOS design. This chip performs MPEG-4 Simple Profile Level 2(Simple@L2) and H.263 base mode. Its contains 388,885 gates, 662k bits memory, and the chip size was 9.7 mm x 9.7 mm which was fabricated using 0.35 micron 3-layers metal CMOS technology.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.253-256
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• 2001

This paper introduces the design of high-speed analog- to-digital converter for high-definition TV, camcorders, portable equipments and implemented in a 0.65${\mu}{\textrm}{m}$ CMOS technology. Key circuits developed for low power and high speed A/D converter are a dynamic comparator that consumes no static power, a source follower buffered op amp that achives wide bandwidth using large input devices. The converter achieves low power dissipation of 40-mW at 3.3-V power supply. Measured performance includes 0.53 LSB of INL and 0.48 LSB of DNL while sampling at 60MHz.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1601-1602
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• 2006

A cascode low noise amplifier(LNA) for a 2.45GHz RFID reader is designed using 0.25um CMOS technology. There are four LNA design techniques applied to the cascode topology. In this paper, power-constrained simultaneous noise and input matching(PCSNIM) technique is used for low power consumption and achieving the noise matching and input matching simultaneously. Simulation results demonstrate a noise figure of 2.75dB, a power gain of 10.17dB, and a dissipation power of 8.65mW with 1V supply.

• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.317-328
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• 2016

Over the past few decades, CMOS current comparators have been used in a wide range of applications, including analogue circuits, MVL (multiple-valued logic) circuits, and various electronic products. A current comparator is generally used in an ADC (analog-to-digital) converter of sensors and similar devices, and several techniques and approaches have been implemented to design the current comparator to improve performance. To this end, this paper presents a bibliographical survey of recently-published research on different current comparator topologies for low-power and high-speed applications. Moreover, several aspects of the CMOS current comparator are discussed regarding the design implementation, parameters, and performance comparison in terms of the power dissipation and operational speed. This review will serve as a comparative study and reference for researchers working on CMOS current comparators in low-power and high-speed applications.