• 한국표면공학회지
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• 제44권6호
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• pp.264-268
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• 2011

The Molybedenium thin film is generally used on back contact material of CIGS solar cell due to low electrical resistivity and stable thermal expansion coefficient. The Mo thin films deposited on si wafer by the magnetron sputtering method. The research focused on the variation of electrical resistivity of films which deposited with various working pressure at the target power of 2.0 kW(8.4 W/). The lowest resistivity of Mo thin film showed $9.0{\mu}O$-cm at pressure of 1.5 mTorr. However, working pressure increasing up to 50 mTorr, resistivities were highly increased. The results showed that the conductivity of Mo films depended on growing structures and defects in deposition process. Surface morphology, porosity, grain size, oxidation, and bonding structures were analysed by SEM, AFM, spectroscopic ellipsometry (SE), XRD, and XPS.

• 한국생산제조학회지
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• 제23권6호
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• pp.533-538
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• 2014

We fabricated grooved mushroom structures with anisotropic wettability on silicon substrates using basic MEMS processes. The geometry of these grooved mushroom structures could be changed by controlling the additional IPA solution during Si etching by TMAH solution. To understand anisotropic wettability, contact angles (CAs) of hexadecane droplets were measured in the orthogonal and parallel directions to grooved lines. The CA measurement results displayed anisotropic wetting on the grooved mushroom structures. However, specimens with $80{\mu}m$ distance between top layers displayed isotropic and superoleophobic wetting. This study demonstrates that the thickness of the top layer is more critical than the width or height of the ridge when determining the wettability of organic solvent. Despite the wide distance between top layers ($80{\mu}m$), the specimen with a thin top layer (100 nm) showed highly anisotropic wetting and low CA due to the pinning of droplets at the edge of the top layer.

• 반도체디스플레이기술학회지
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• 제10권4호
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• pp.65-70
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• 2011

These days, printed electronics attract attention from electronics industry. In this paper, the fabrication of the fine patterns by Near Field Electro Spinning (NFES) was studied by using Ag ink on silicon wafer (substrate). Two types of ink, the high viscous ink Ag-200 and low viscous ink Ag-15, were used. The fine and uniform patterns were easily fabricated by using Ag-200 because jet breakup is less occurred in high viscosity solution. As increasing flow rate of solution, aspect ratio of Ag pattern decreased. And there was optimum applied voltage for fine pattern. In case of Ag-200, the optimum applied voltage was about 2.02KV. When pattern was fabricated by NFES, the pattern width and height were affected by many factors such as viscosity, flow rate of solution, applied voltage etc.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2003년도 하계학술연구발표회 및 한.일 공동심포지엄
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• pp.194-194
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• 2003

As a result of the recent miniaturization an enhancement in the performance of thin film inductors and thin film transformers, there are increased demands for the thin films with high magnetic permeability in the high frequency range, high saturation magnetization, in high electrical resistivity, and low coercive force. In order to improve high frequency properties, we will investigate anisotropy field by shape and size of pattern. The Fe-Al-O thin films of 16mm and 1 $\mu\textrm{m}$ thickness were deposited on Si wafer, using RF magnetron reactive sputtering technique with the mixture of argon and oxygen gases. The fabricating conditions are obtained in the working partial pressure of 2mTorr, O$_2$ partial pressure of 5%, input power of 400W, and Al pellets on an Fe disk with purity of 99,9%. Magnetic properties of the continuous films as followed: the 4$\pi$M$\_$s/ of 19.4kG, H$\_$c/ of 0.6Oe, H$\_$k/ of 6.0Oe and effective permeability of 2500 up to 100㎒ were obtained. In this work, we expect to enhance effect of magnetic anisotropy on patterned of Fe-Al-O thin films.

• 한국재료학회지
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• 제29권11호
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• pp.720-726
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• 2019

Recently, research on cost reduction and efficiency improvement of crystalline silicon(c-Si) photovoltaic(PV) module has been conducted. In order to reduce costs, the thickness of solar cell wafers is becoming thinner. If the thickness of the wafer is reduced, cracking of wafer may occur in high temperature processes during the c-Si PV module manufacturing process. To solve this problem, a low temperature process has been proposed. Conductive paste(CP) is used for low temperature processing; it contains Sn57.6Bi0.4Ag component and can be electrically combined with solar cells and ribbons at a melting point of $150^{\circ}C$. Use of CP in the PV module manufacturing process can minimize cracks of solar cells. When CP is applied to solar cells, the output varies with the amount of CP, and so the optimum amount of CP must be found. In this paper, in order to find the optimal CP application amount, we manufactured several c-Si PV modules with different CP amounts. The amount control of CP is fixed at air pressure (500 kPa) and nozzle diameter 22G(outer diameter 0.72Ø, inner 0.42Ø) of dispenser; only speed is controlled. The c-Si PV module output is measured to analyze the difference according to the amount of CP and analyzed by optical microscope and Alpha-step. As the result, the optimum amount of CP is 0.452 ~ 0.544 g on solar cells.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.319-325
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• 2017

Through silicon via (TSV) technology is extensively used in 3D IC integrations. The special structure of the TSV is realized by CMP (Chemically Mechanical Polishing) process with a high Cu removal rate and, low dishing, yielding fine topography without defects. In this study, we investigated the electrochemical behavior of copper slurries with various inhibitors in the Cu CMP process for advanced TSV applications. One of the slurries was carried out for the most promising process with a high removal rate (${\sim}18000{\AA}/Min$ @ 3 psi) and low dishing (${\sim}800{\AA}$), providing good microstructure. The effects of pH value and $H_2O_2$ concentration on the slurry corrosion potential and Cu static etching rate (SER) were also examined. The slurry formula with a pH of 6 and 2% $H_2O_2$, hadthe lowest SER (${\sim}75{\AA}/Min$) and was the best for TSV CMP. A novel Cu TSV CMP process was developed with two CMPs and an additional annealing step after some of the bulk Cu had been removed, effectively improving the condition of the TSV Cu surface and preventing the formation of crack defects by variations in wafer stress during TSV process integration.

• 센서학회지
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• 제24권4호
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• pp.264-269
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• 2015

An infrared (IR) bolometer measures the change of resistance by absorbing incident IR radiation and generates a signal as a function of the radiation intensity. Since a bolometer requires temperature stabilization and light filtering except for the infrared rays, it is essential for the device to be packaged meeting conditions that above mentioned. Minimization of heat loss is needed in order to stabilize temperature of bolometer. Heat loss by conduction or convection requires a medium, so the heat loss will be minimized if the medium is a vacuum. Therefore, vacuum packaging for bolometer is necessary. Another important element in bolometer packaging is germanium (Ge) window, which transmits IR radiation to heat the bolometer. To ensure a complete transmittance of IR light, anti-reflection (AR) coatings are deposited on both sides of the window. Although the transmittance of Ge window is high for IR rays, it is difficult to use frequently in low-price IR bolometer because of its high price. In this paper, we fabricated IR window by utilizing silicon (Si) substrate instead of Ge in order to reduce the cost of bolometer packaging. To enhance the IR transmittance through Si substrate, it is textured using Reactive Ion Etching (RIE). The texturing process of Si substrate is performed along with the change of experimental conditions such as gas ratio, pressure, etching time and RF power.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2009년도 추계학술발표대회
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• pp.36.2-36.2
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• 2009

Low dielectric materials have been great attention in the semiconductor industry to develop high performance interlayer dielectrics with low k for Cu interconnect technology. In our study, the dielectric properties of SiOC /SiO2 thin film derived from polyphenylcarbosilane were investigated as a potential interlayer dielectrics for Cu interconnect technology. Polyphenylcarbosilane was synthesized from thermal rearrangement of polymethylphenylsilane around $350^{\circ}C{\sim}430^{\circ}C$. Characterization of synthesized polyphenylcarbosilane was performed with 29Si, 13C, 1H NMR, FT-IR, TG, XRD, GPC and GC analysis. From FT-IR data, the band at 1035 cm-1 is very strong and assigned to CH2 bending vibration in Si-CH2-Si group, indicating the formation of the polyphenylcarbosilane. Number average of molecular weight (Mn) of the polyphenylcarbosilane synthesized at $400^{\circ}C$ for 6hwas 2, 500 and is easily soluble in organic solvent. SiOC/SiO2 thin film was fabricated on ton-type silicon wafer by spin coating using 30wt % polyphenylcarbosilane incyclohexane. Curing of the film was performed in the air up to $400^{\circ}C$ for 2h. The thickness of the film is ranged from $1{\mu}m$ to $1.7{\mu}m$. The dielectric constant was determined from the capacitance data obtained from metal/polyphenylcarbosilane/conductive Si MIM capacitors and show a dielectric constant as low as 2.5 without added porosity. The SiOC /SiO2 thin film derived from polyphenylcarbosilane shows promising application as an interlayer dielectrics for Cu interconnect technology.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.143.1-143.1
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• 2016

Ge is a promising candidate to replace Si in MOSFET because of its superior carrier mobility, particular that of the hole. However Ge oxide is thermodynamically unstable. At elevated temperature, GeO is formed at the interface of Ge and GeO2, and its formation increases the interface defect density, degrading its device performance. In search for a method to surmount the problem, we investigated Ge oxidation through an inert capped oxide layer. For this work, we prepared low doped n-type Ge(100) wafer by removing native oxide and depositing a capping layer, and show that GeO2 interface can be successfully grown through the capping layer by thermal oxidation in a furnace. The thickness and quality of thus grown GeO2 interface was examined by ellipsometry, XPS, and AFM, along with I-V and C-V measurements performed at 100K to 300K. We will present the result of our investigation, and provide the discussion on the oxide growth rate, interface state density and electrical characteristics in comparison with other studies using the direct oxidation method.

• 한국전기전자재료학회논문지
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• 제24권2호
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• pp.156-161
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• 2011

The present study introduces a novel wet etching technique for nanostructure fabrications which usually requires low surface roughness. Using the current method, acquired profiles were smooth even in the nanoscale, which cannot be easily achieved with conventional wet or dry etching methods. As one of the most popular single crystal silicon etchant, potassium hydroxide (KOH) solution was used as a base solvent and two additives, antimony trioxide (Sb2O3) and ethyl alcohol were employed in. Four experimental parameters, concentrations of KOH, Sb2O3, and ethyl alcohol and temperature were optimized at 60 wt.%, 0.003 wt.%, 10 v/v%, and $23^{\circ}C$, respectively. Effects of additives in KOH solution were investigated on the profiles in both (110) and (111) planes of single crystal silicon wafer. The preliminary results show that additives play a critical role to decrease etch rate significantly down to ~2 nm/min resulting in smooth side wall profiles on (111) plane and enhanced surface roughness.