• 전자공학회논문지A
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• 제29A권8호
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• pp.56-62
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• 1992

This paper is analyzed the charge trapping and electrical properties of 0(Oxide), NO(Nitrided oxide) and ONO(Reoxidized nitrided oxide) as dielectric films in MIS structures. We have processed bottom oxide and top oxide by the thermal method, and nitride(Si$_{3}N_{4}$) by the LPCVD(Low Pressure Chemical Vapor Deposition) method on P-type(100) Silicon wafer. We have studied the charge trapping properties of the dielectrics by using a computer controlled DLTS system. All of the dielectric films are shown peak nearly at 300K. Those are bulk traps. Many trap densities which is detected in NO films, but traps. Many trap densities which is detected in NO films. Varing the nitride thickness, the trap densities of thinner nitride is decreased than the thicker nitride. Finally we have found that trap densities of ONO films is affected by nitride thickness.

• ETRI Journal
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• 제17권4호
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• pp.1-12
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• 1996

A novel body-tied silicon-on-insulator(SOI) n-channel metal-oxide-semiconductor field-effect transistor with grounded body electrode named GBSOI nMOSFET has been developed by wafer bonding and etch-back technology. It has no floating body effect such as kink phenomena on the drain current curves, single-transistor latch and drain current overshoot inherent in a normal SOI device with floating body. We have characterized the interface trap density, kink phenomena on the drain current ($I_{DS}-V_{DS}$) curves, substrate resistance effect on the $I_{DS}-V_{DS}$ curves, subthreshold current characteristics and single transistor latch of these transistors. We have confirmed that the GBSOI structure is suitable for high-speed and low-voltage VLSI circuits.

• 센서학회지
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• 제8권1호
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• pp.32-37
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• 1999

본 연구에서는 다공질 실리콘층을 감습재료로 사용한 메사 구조를 갖는 정전용량형 습도센서를 제작하고 그 특성을 평가하였다. 센서의 구조적 특징은 기존의 웨이퍼 상하에 전극을 배치한 구조와 달리, 두 전극의 위치를 시료의 상부에 두도록 함으로서 집적화를 용이하게 할 뿐만 아니라, 하부 기판과 다른 접합영역으로부터 발생하는 정전용량의 영향을 차단하여 출력신호의 신뢰성을 개선하였다. 이를 위해 산화 다공질 실리콘의 형성과 빠른 에칭특성을 이용하여 메사 구조를 만들고, 다공질 실리콘층의 선택적 형성과 감광막을 마스크막으로 이용하여 다공질 실리콘층을 국부적으로 형성하였다. 그리고 완성된 시료에 대해 상온에서 55 - 90% 이상의 상대 습도 범위에서 감습특성을 측정하였다. 그 결과, 습도가 증가했을 때 측정된 정전용량은 전체적으로 단조 증가하였으며, 120 Hz의 저주파수에서 측정했을 때 정전용량이 300%이상 증가하는 높은 변화를 보였다

• 한국전기전자재료학회논문지
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• 제29권12호
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• pp.750-758
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• 2016

For the channel doping of shallow junction and retrograde well formation in CMOS, indium can be implanted in silicon. The retrograde doping profiles can serve the needs of channel engineering in deep MOS devices for punch-through suppression and threshold voltage control. Indium is heavier element than B, $BF_2$ and Ga ions. It also has low coefficient of diffusion at high temperatures. Indium ions can be cause the erode of wafer surface during the implantation process due to sputtering. For the ultra shallow junction, indium ions can be implanted for p-doping in silicon. UT-MARLOWE and SRIM as Monte carlo ion-implant models have been developed for indium implantation into single crystal and amorphous silicon, respectively. An analytical tool was used to carry out for the annealing process from the extracted simulation data. For the 1D (one-dimensional) and 2D (two-dimensional) diffused profiles, the analytical model is also developed a simulation program with $C^{{+}{+}}$ code. It is very useful to simulate the indium profiles in implanted and annealed silicon autonomously. The fundamental ion-solid interactions and sputtering effects of ion implantation are discussed and explained using SRIM and T-dyn programs. The exact control of indium doping profiles can be suggested as a future technology for the extreme shallow junction in the fabrication process of integrated circuits.

• 한국진공학회지
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• 제22권5호
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• pp.238-244
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• 2013

태양전지 제조공정에서 열처리로 레이저를 사용하는 도핑공정은 태양전지의 성능을 결정짓는 중요한 요소이다. 그러나 퍼니스를 이용하는 공정에서는 선택적으로 고농도(Heavy) 도핑영역을 형성하기가 어렵다. 레이저를 사용한 선택적 도핑의 경우 고가의 레이저 장비가 요구되어지며, 레이저 도핑 후 고온의 에너지로 인한 웨이퍼의 구조적 손상 문제가 발생된다. 본 연구는 저가이면서 코로나 방전 구조의 대기압 플라즈마 소스를 제작하였고, 이를 통한 선택적 도핑에 관한 연구를 하였다. 대기압 플라즈마 제트는 Ar 가스를 주입하여 수십 kHz 주파수를 인가하여 플라즈마를 발생시키는 구조로 제작하였다. P-type 웨이퍼(Cz)에 인(P)이 shallow 도핑 된(120 Ohm/square) PSG (Phosphorus Silicate Glass)가 제거되지 않은 웨이퍼를 사용하였다. 대기압 플라즈마 도핑 공정 처리시간은 15 s와 30 s이며, 플라즈마 전류는 40 mA와 70 mA로 처리하였다. 웨이퍼의 도핑프로파일은 SIMS (Secondary Ion Mass Spectroscopy)측정을 통하여 분석하였으며, 도핑프로파일로 전기적 특성인 면저항(sheet resistance)을 파악하였다. 도펀트로 사용된 PSG에 대기압 플라즈마 제트로 도핑공정을 처리한 결과 전류와 플라즈마 처리시간이 증가됨에 따라 도핑깊이가 깊어지고, 면저항이 향상하였다. 대기압 플라즈마 도핑 후 웨이퍼의 표면구조 손상파악을 위한 SEM (Scanning Electron Microscopy) 측정결과 도핑 전과 후 웨이퍼의 표면구조는 차이가 없음을 확인하였으며, 대기압 플라즈마 도핑 폭도 전류와 플라즈마 처리시간이 증가됨에 따라 증가하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.228-228
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• 2010

본 연구에서는 공진주파수 수식을 이용한 MATLAB과 Modal 해석법을 사용한 ANSYS로 공진주파수 특성을 시뮬레이션 하였다. 외팔보의 시뮬레이션 결과에서는 길이가 길어짐에 따라, 또는 proof mass의 크기가 커짐에따라 공진주파수 특성이 낮아지는 결과가 나타났다. 따라서 본 실험에서의 외팔보는 낮은 공진 주파수를 가지기 위해 Si proof mass를 사용하여 제작하였다. 외팔보 소자는 Silicon-on-insulator wafer를 사용하여 SiO2/Ti/Pt/PZT/Pt 박막을 증착하였고, 마스크를 사용한 식각 공정으로 제작하였다. 이때의 MATLAB, ANSYS 시뮬레이션 결과와 실험에서 제작된 소자는 유사한 공진주파수 특성을 나타내었다.

• ETRI Journal
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• 제34권2호
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• pp.226-234
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• 2012

The novelty of this study resides in the fabrication of stoichiometric and stress-reduced $Si_3N_4/SiO_2/Si_3N_4$ triple-layer membrane sieves. The membrane sieves were designed to be very flat and thin, mechanically stress-reduced, and stable in their electrical and chemical properties. All insulating materials are deposited stoichiometrically by a low-pressure chemical vapor deposition system. The membranes with a thickness of 0.4 ${\mu}m$ have pores with a diameter of about 1 ${\mu}m$. The device is fabricated on a 6" silicon wafer with the semiconductor processes. We utilized the membrane sieves for plasma separations from human whole blood. To enhance the separation ability of blood plasma, an agarose gel matrix was attached to the membrane sieves. We could separate about 1 ${\mu}L$ of blood plasma from 5 ${\mu}L$ of human whole blood. Our device can be used in the cell-based biosensors or analysis systems in analytical chemistry.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.390-390
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• 2010

Superconducting proximity effects of Nb/Si(111) were investigated with scanning tunneling microscopy(STM) and scanning tunneling spectroscopy(STS). A highly-doped($0.002\;{\omega}{\diamondsuit}cm$) Si wafer pieces were used as substrate and Nb source was thermally evaporated onto the atomically clean silicon substrate. The temperature of the silicon sample was held at $600^{\circ}C$ during the niobium deposition. And the sample was annealed at $600^{\circ}C$ for 30 minutes additionally. Volmer-Weber growth mode is preferred in Nb/Si(111) at the sample temperature of $600^{\circ}C$. With proper temperature and annealing time, we can obtain Nb islands of lateral size larger than Nb coherence length(~38nm). And outside of the islands, bare Si($7{\times}7$) reconstructed surface is exposed due to the Volmer-Weber Growth mode. STS measurement at 5.6K showed that Nb island have BCS-like superconducting gap of about 2mV around the Fermi level and the critical temperature is calculated to be as low as 6.1K, which is lower than that of bulk niobium, 9.5K. This reduced value of superconducting energy gap indicates suppression of superconductivity in nanostructures. Moreover, the superconducting state is extended out of the Nb island, over to bare Si surface, due to the superconducting proximity effect. Spatially-resolved scanning tunneling spectroscopy(SR-STS) data taken over the inside and outside of the niobium island shows gradually reduced superconducting gap.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.111-111
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• 2007

Further scaling the semiconductor devices down to low dozens of nanometer needs the extremely shallow depth in junction and the intentional counter-doping in the silicon gate. Conventional ion beam ion implantation has some disadvantages and limitations for the future applications. In order to solve them, therefore, plasma source ion implantation technique has been considered as a promising new method for the high throughputs at low energy and the fabrication of the ultra-shallow junctions. In this paper, we study about the effects of DC bias and base pressure as a process parameter. The diluted mixture gas (5% $PH_3/H_2$) was used as a precursor source and chamber is used for vacuum pressure conditions. After ion doping into the Si wafer(100), the samples were annealed via rapid thermal annealing, of which annealed temperature ranges above the $950^{\circ}C$. The junction depth, calculated at dose level of $1{\times}10^{18}/cm^3$, was measured by secondary ion mass spectroscopy(SIMS) and sheet resistance by contact and non-contact mode. Surface morphology of samples was analyzed by scanning electron microscopy. As a result, we could accomplish the process conditions better than in advance.

• Journal of Information Display
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• 제6권2호
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• pp.16-18
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• 2005

Hybrid insulator pentacene thin film transistors (TFTs) are fabricated with thermally grown oxide and cross-linked polyvinylalcohol (PVA) including surface treatment by dilute ploymethylmethacrylate (PMMA) layer on $n^+$ doped silicon wafer. Through the optimization of $SiO_2$ layer thickness in hybrid insulator structure, carrier mobility is increased to more than 35 times than that of the TFT which has only a gate insulator of $SiO_2$ at the same electric field. The carrier mobility of $1.80cm^2$/V-s, subthreshold swing of 1.81 V/decade, and $I_{on}/I_{off}$ current ratio> $1.10{\times}10^5$ are obtained less than -30 V bias condition. The result is one of the best reported performances of pentacene TFTs with hybrid insulator including cross-linked PVA layer as a gate insulator at relatively low voltage operation.