• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.2C
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• pp.175-180
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• 2009

When we apply the LDPC code for high density optical storage channel, it is necessary to make an algorithm that the modulation code decoder must feed the LDPC decoder soft-valued information because LDPC decoder exploits soft values using the soft input. Therefore, we propose the soft-input soft-output run-length limited 17PP decoding algorithm and compare performance of LDPC codes. Consequently, we found that the proposed soft-input soft-output decoding algorithm using 17PP is 0.8dB better than the soft-input soft-output decoding algorithm using (1, 7) RLL.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.419-426
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• 2014

This paper proposes a high-throughput encoding process and encoder architecture for quasi-cyclic low-density parity-check codes in IEEE 802.11ac standard. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase the encoding throughput. A low complexity cyclic shifter is also proposed to minimize the hardware overhead of combinational logic in the encoder architecture. In IEEE 802.11ac systems, the proposed encoder is rate compatible to support various code rates and codeword block lengths. The proposed encoder is implemented with 130-nm CMOS technology. For (1944, 1620) irregular code, 7.7 Gbps throughput is achieved at 100 MHz clock frequency. The gate count of the proposed encoder core is about 96 K.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.5C
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• pp.498-504
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• 2009

A high-performance low-complexity decoding algorithm for LDPC codes is proposed in this paper, which has the advantages of both bit-flipping (BF) algorithm and sum-product algorithm (SPA). The proposed soft bit-flipping algorithm requires only simple comparison and addition operations for computing the messages between bit and check nodes, and the amount of those operations is also small. By increasing the utilization ratio of the computed messages and by adopting nonuniform quantization, the signal-to-noise ratio (SNR) gap to the SPA is reduced to 0.4dB at the frame error rate of 10-4 with only 5-bit assignment for quantization. LDPC codes with high column or row weights, which are not suitable for the SPA decoding due to the complexity, can be practically implemented without much worsening the error performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.8C
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• pp.522-528
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• 2011

The iterative detection and decoding (IDD) has been shown to dramatically improve the bit error rate (BER) performance of the multiple-input multiple-output (MIMO) communication systems. However, these techniques require a high computational complexity since it is required to compute the soft decisions for each bit. In this paper, we show IDD comprised of sphere decoder with low-density parity check (LDPC) codes and present the tree search strategy, called a layer symbol search (LSS), to obtain soft decisions with a low computational complexity. In addition, an adaptive early termination is proposed to reduce the computational complexity during an iteration between an inner sphere decoder and an outer LDPC decoder. It is shown that the proposed approach can achieve the performance similar to an existing algorithm with 70% lower computational complexity compared to the conventional algorithms.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11a
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• pp.535-537
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• 2005

디지털 신호 및 전송부호의 오류검출에는 예전부터 패리티 체크가 사용되어 왔다. 그러나 패리티 체크 기법은 구현 및 알고리즘이 단순, 간결한 우수성이 있지만 특정 데이터 비트의 경우 오류 검출이 불가능하다는 문제점을 가지고 있다. 이후 패리티 체크 기법은 해밍 코드 및 채널 오류 정정을 위한 LDPC 코드와 같은 다양한 오류검출 및 정정 알고리즘에 적용되어 발전되어 왔으며, 그 중 LDPC 코드의 bit-flipping 알고리즘에서는 패리티 기법을 반복적으로 적용하는 방식을 택하고 있다. 본 논문에서는 이러한 채널 오류 정정을 위한 LDPC의 bit-flipping 알고리즘을 이차원 코드에 적용하고, 이 때 bit-flipping 알고리즘이 가지고 있는 문제점을 보완할 수 있는 개선된 LDPC 코드를 제안한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.12
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• pp.1742-1744
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• 2016

In this letter, we prove equivalence of the Binary perturbation and Afterburner LDPC decoder that are proposed for improving the decoding performance in short length LDPC codes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.10C
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• pp.936-941
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• 2003

Density evolution was developed as a method for computing the capacity of low-density parity-check(LDPC) codes under the sum-product algorithm [1]. Based on the assumption that the passed messages on the belief propagation model can be approximated well by Gaussian random variables, a modified and simplified version of density evolution technique was introduced in [2]. Recently, the min-sum algorithm was applied to the density evolution of LDPC codes as an alternative decoding algorithm in [3]. Next question is how the min-sum algorithm is combined with a Gaussian approximation. In this paper, the capacity of various rate LDPC codes is obtained using the min-sum algorithm combined with the Gaussian approximation, which gives a simplest way of LDPC code analysis. Unlike the sum-product algorithm, the symmetry condition [4] is not maintained in the min-sum algorithm. Therefore, the variance as well as the mean of Gaussian distribution are recursively computed in this analysis. It is also shown that the min-sum threshold under a gaussian approximation is well matched to the simulation results.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.3-10
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• 2015

Application of polar codes to rate-adaptive asymmetric Slepian-Wolf coding is considered. We propose a method of constructing polar codes which supports rate adaptivity. The proposed polar distributed source coding with successive cancellation list decoding performs closer to the Slepian-Wolf bound than the low density parity check accumulate (LDPCA) codes in the same framework.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2367-2372
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• 2015

One of various low-density parity-check(LDPC) codes that has been adopted in many communication standards due to its error correction ability is a quasi-cyclic LDPC(QC-LDPC) code, which leads to comparable decoder complexity. One of the main blocks in the QC-LCDC code decoder is a multi-size circular shifter(MSCS) that can perform various size rotation. The MSCS can be implemented with many structures, one of which is based on Banes network. The Benes network structure can perform the normal MSCS operation efficiently, but it cannot use the properties coming from specifications like rotation sizes. This paper proposesd a scheme where the Benes network structure can use the rotation size property with the modification of the control signal generation. The proposed scheme is applied to the MSCS of IEEE 802.16e WiMAX QC-LDPC decoder to reduce the number of MUXes and the critical path delay.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.9C
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• pp.683-690
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• 2008

By using inherent stopping criteria of LDPC codes, the average number of iterations can be substantially reduced at high signal to noise ratio (SNR). However, we encounter a problem when hybrid automatic repeat request (H-ARQ) systems are applied. Frequent failures of decoding at low SNR region imply that the decoder leaches the maximum number of iterations frequently and thus the decoding complexity increases. In this paper, we propose a combination of stopping criteria using the syndrome weight of tentative codeword. By numerical analysis, it is shown that the decoding complexity of given H-ARQ system is reduced by 70-80% with the proposed algorithms.