• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.593-596
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• 2004

This paper presents a low power design of the embedded 3D graphics rendering processor with the double span processing stage. The increase of hardware complexity by using the double span processing stage is ignorable. And the performance is equal to the rendering processor with the single span processing stage. It reduces the power consumption by using different clock frequencies.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.754-758
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• 2002

In the fuel-cell electric vehicle system, the low-voltage output of unit fuel-cell demands a number of cells to be stacked In series to produce a DC link voltage which is high enough to drive the vehicle inverter system. However, this increases the complexity of the fuel-cell control system. This paper presents a design of high-efficiency boost converter employing the average current-mode control, which is able to convert a low voltage of a fuel-cell generator with a small number of unit cells to a stable and high DC link voltage for electric vehicle applications.

• 한국국방경영분석학회지
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• 제27권1호
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• pp.73-88
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• 2001

Designing high quality products and processes at a low cost is central technological and economic challenge to the engineer. The combination of engineering concepts and statistical implementations offered by Taguchi\`s off-line design technique has proven t be invaluable. By examining some deficiencies in designs from the Taguchi\`s highly fractional, orthogonal main effect plan based on orthogonal arrays, alternative method is proposed. The maximum resolution or the minimum aberration criterion is commonly used for selecting 2$^{n-m}$ fractional designs. We present new high resolution (low aberration) linear graphs to simplify the complexity of selecting designs with desirable statistical properties. The new linear graphs approach shows a substantial improvement over Taguchi\`s linear graphs and other related graphical methods for planning experiment. The new set of linear graphs will allow the experimenter to maintain the simple approach suggested by Taguchi while obtaining the best statistical properties of the resulting design such as minimum aberration as a by-product without dependency on complicated computational algorithm or additional statistical training.g.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2019년도 전력전자학술대회
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• pp.139-141
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• 2019

Capacitive power transfer has an advantage in the simplicity of the energy link structure. So, the conventional phase -shift full bridge sometime is not always the best choice because of its complexity and high cost. On the other hand, the link capacitance is usually very low and requires high-frequency operation, but, the series resonant converter loses zero-voltage switching feature in the light load condition, which makes the switching loss high especially in CPT system. The paper proposes a new low-cost topology based on asymmetric half-bridge to achieve simplicity as well as wide zero voltage switching range. The design procedure is presented, and circuit operations are analyzed and verified by simulation.

• ETRI Journal
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• 제45권3호
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• pp.534-542
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• 2023

The large amount of secondary effects in complementary metal-oxide-semiconductor technology limits its application in the ultra-nanoscale region. Circuit designers explore a new technology for the ultra-nanoscale region, which is the quantum-dot cellular automata (QCA). Low-energy dissipation, high speed, and area efficiency are the key features of the QCA technology. This research proposes a novel, low-complexity, QCA-based one-bit digital comparator circuit for the ultra-nanoscale region. The performance of the proposed comparator circuit is presented in detail in this paper and compared with that of existing designs. The proposed QCA structure for the comparator circuit only consists of 19 QCA cells with two clock phases. QCA Designer-E and QCA Pro tools are applied to estimate the total energy dissipation. The proposed comparator saves 24.00% QCA cells, 25.00% cell area, 37.50% layout cost, and 78.11% energy dissipation compared with the best reported similar design.

• 전기학회논문지
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• 제66권9호
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• pp.1402-1408
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• 2017

Recently, services for personal biometric data analysis based on real-time monitoring systems has been increasing and many of them have focused on recognition of emotions. In this paper, we propose a classification model to classify anxiety emotion using biometric data actually collected from people. We propose to deploy the support vector machine to build a classification model. In order to improve the classification accuracy, we propose two data pre-processing procedures, which are normalization and data deletion. The proposed algorithms are actually implemented based on Real-time Traffic Flow Measurement structure, which consists of data collection module, data preprocessing module, and creating classification model module. Our experiment results show that the proposed classification model can infers anxiety emotions of people with the accuracy of 65.18%. Moreover, the proposed model with the proposed pre-processing techniques shows the improved accuracy, which is 78.77%. Therefore, we can conclude that the proposed classification model based on the pre-processing process can improve the classification accuracy with lower computation complexity.

• Journal of Communications and Networks
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• 제10권1호
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• pp.28-37
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• 2008

In this paper, we investigate the problem of minimizing the average transmission power of users while guaranteeing the average delay constraints in time-varying uplink channels. We design a scheduler that selects a user for transmission and determines the transmission rate of the selected user based on the channel and backlog information of users. Since it requires prohibitively high computation complexity to determine an optimal scheduler for multi-user systems, we propose a low-complexity scheduling scheme that can achieve near-optimal performance. In this scheme, we reduce the complexity by decomposing the multiuser problem into multiple individual user problems. We arrange the probability of selecting each user such that it can be determined only by the information of the corresponding user and then optimize the transmission rate of each user independently. We solve the user problem by using a dynamic programming approach and analyze the upper and lower bounds of average transmission power and average delay, respectively. In addition, we investigate the effects of the user selection algorithm on the performance for different channel models. We show that a channel-adaptive user selection algorithm can improve the energy efficiency under uncorrelated channels but the gain is obtainable only for loose delay requirements in the case of correlated channels. Based on this, we propose a user selection algorithm that adapts itself to both the channel condition and the backlog level, which turns out to be energy-efficient over wide range of delay requirement regardless of the channel model.

• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2001년도 추계학술대회논문집 II
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• pp.1207-1214
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• 2001

The paper deals with the computational approach in analysis and design of pantograph panhead strips of high-speed railway in aerodynamic and aeroacoustic concerns. Pantograph is an equipment such that the electric power is supplied from catenary system to train. Due to the nature of complexity in high-speed fluid flow, turbulence and downstream vortices result in the instability in the aerodynamic contact between panhead strips and catenary system, and consequently generate the considerable levels of flow-induced sound. In this paper, based on the preceding low speed wind-tunnel test and simulations, the aerodynamic and aeroacoustic characteristics in low speed are analyzed.

• 대한전자공학회논문지SD
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• 제42권9호
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• pp.51-60
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• 2005

효율적인 암호 시스템의 설계는 환경에 적합한 유한체 연산이 뒷받침되어야 한다 특히 유한체에서의 역원 연산은 다른 연산에 비해 가장 많은 수행시간을 소비하므로, 개선에 대한 연구가 활발히 진행되고 있다. 본 논문에서는 다항식 기저를 기반으로 Extended binary god algorithm (EBGA)를 이용한 유한체 $GF(2^m)$에서의 고속 역원 알고리즘을 제안한다. 제안된 역원 알고리즘은 EBGA보다 $18.8\%$, Montgomery inverse algorithm (MIA)보다 $45.9\%$ 적은 수행횟수를 가진다. 또한 기존에 제안된 시스톨릭 어레이 구조 (Systolic array structure)는 유한체 차수 m이 증가하는 경우 많은 하드웨어 리소스가 요구된다. 따라서 스마트 카드나 모바일 폰 등과 같은 경량화와 저전력이 요구되는 환경에는 적용하기 힘들다. 본 논문에서는 경량화된 암호 시스템 환경을 바탕으로 공간복잡도가 적으면서 동기화된 연산을 수행하는 새로운 하드웨어 구조를 제시한다. 본 논문에서 제안된 하드웨어 구조는 유한체 $GF(2^m)$에서의 역원을 계산하기 위해 기존의 알고리즘보다 적은 덧셈 연산과 모듈러 감산 연산을 포함하고 있으며, 유한체 $GF(2^m)$와 GF(p)에 적용이 가능한 통합된 역원기이다.

• 한국통신학회논문지
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• 제31권3A호
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• pp.282-290
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• 2006

본 논문에서는 2.45GHz 대역 IEEE 802.15.4 LR-WPAN(Low-Rate Wireless Personal Area Network; ZigBee) 시스템의 수신기를 위한 개선된 방식의 Timing estimator의 알고리즘을 제안한다. 저가 구현을 지향하는 LR-WPAN 시스템의 특성상 고가의 오실레이터를 사용할 수 없으므로 반송파 중심 주파수의 80ppm에 해당하는 주파수 옵셋 환경에서 안정된 동작이 가능한 Timing estimator 알고리즘이 요구된다. 본 논문에서는 이러한 수신 환경을 고려하여 Multiple delay differential filter를 적용함으로써 주파수 옵셋에 대한 강인성 및 수신 성능의 안정성을 증대시켰으며, Multiple delay differential filter의 출력 신호에 대한 reference 신호의 상관 결과가 I-channel 에만 국한되는 특성을 이용하여 일반적인 noncoherent 방식 대신 coherent 방식의 correlator를 적용함으로써 non-coherent 방식의 제곱 손실을 제거하여 검출 성능을 향상시킴과 동시에 복잡도를 감소시켜 초소형, 저전력, 저가를 지향하는 LR-WPAM 수신기에 보다 적합하도록 설계하였다. 다양한 채널 환경에서의 성능정가를 통하여 제안된 알고리즘이 differential detection 기반의 noncoherent 방식보다 평균적으로 2dB의 향상된 성능을 보임을 입증하였다.