• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.131-137
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• 2013

The barrel distortion makes serious problems in a wide-angle camera employing a lens of a short focal length. This paper presents a low-complexity hardware architecture for a real-time barrel distortion corrector and its implementation. In the proposed barrel distortion corrector, the conventional algorithm is modified so that the correction is performed incrementally, which results in the reduction of the number of required hardware modules for the distortion correction. The proposed barrel distortion corrector has a pipelined architecture so as to achieve a high-throughput correction. The correction rate is 74.86 frames per sec at the operating frequency of 314MHz in a $0.11{\mu}m$ CMOS process, where the frame size is $2048{\times}2048$. The proposed barrel distortion corrector is implemented with 14.3K logic gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12B
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• pp.2391-2400
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• 1999

Vector quantizer (VQ) is an efficient data compression technique for low bit rate applications. However, the major disadvantage of VQ is its encoding complexity which increases dramatically as the vector dimension and bit rate increase. Even though one can use a modified VQ to reduce the encoding complexity, it is nearly impossible to implement such a VQ at a high bit rate or for a large vector dimension because of the enormously large memory requirement for the codebook and the very large training sequence (TS) size. To overcome this difficulty, in this paper we propose a novel structurally constrained VQ for the high bit rate and the large vector dimension cases in order to obtain VQ-level performance. Furthermore, this VQ can be extended to the low bit rate applications. The proposed quantization scheme has a form of feed-forward adaptive quantizer with a short adaptation period. Hence, we call this quantization scheme sample-adaptive product quantizer (SAPQ). SAPQ can provide a 2 ~3dB improvement over the Lloyd-Max scalar quantizers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.9
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• pp.7-13
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• 2010

In this paper, we proposed a processor architecture that is suitable for next generation embedded applications, especially for personal information devices such as smart phones, tablet PC. Latest high performance embedded processors are developed to achieve high clock speed. Because increasing performance makes design more difficult and induces large overhead, architectural evolution in embedded processor field is necessary. Among more enhanced processor types, out-of-order superscalar cannot be a candidate for embedded applications due to its excessive complexity and relatively low performance gain compared to its overhead. Therefore, new architecture with moderate complexity must be designed. In this paper, we developed a low-cost SMT architecture model and compared its performance to other architectures including scalar, superscalar and multiprocessor. Because current personal information devices have a tendency to execute multiple tasks simultaneously, SMT or CMP can be a good choice. And our simulation result shows that the efficiency of SMT is the best among the architectures considered.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.11
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• pp.7582-7588
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• 2015

Noncoherent receivers are favored for block-code-modulated ultrawideband impulse radio (UWB-IR) systems because of their low implementation complexity compared with coherent rake receivers. However, existing noncoherent schemes, such as transmitted reference (TR) systems and averaged differential receivers (ADR), suffer from performance degradation and energy efficiency loss. Codeword matching and signal aggregation (CMSA) is a low complexity noncoherent receiver for UWB-IR. As the frame/symbol duration is shortened to boost data rate, interframe interference (IFI) or intersymbol interference (ISI) occurs and degrades the detection performance of CMSA. In this paper, block coded correlator which consists of the delay components and the reference signal is proposed to improve the performance of the receiver. Simulation results show that the proposed system leads to the better performance compared to the conventional CMSA receiver.

• Journal of Communications and Networks
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• v.12 no.4
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• pp.358-365
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• 2010

We develop a low complexity cooperative diversity protocol for low energy adaptive clustering hierarchy (LEACH) based wireless sensor networks. A cross layer approach is used to obtain spatial diversity in the physical layer. In this paper, a simple modification in clustering algorithm of the LEACH protocol is proposed to exploit virtual multiple-input multiple-output (MIMO) based user cooperation. In lieu of selecting a single cluster-head at network layer, we proposed M cluster-heads in each cluster to obtain a diversity order of M in long distance communication. Due to the broadcast nature of wireless transmission, cluster-heads are able to receive data from sensor nodes at the same time. This fact ensures the synchronization required to implement a virtual MIMO based space time block code (STBC) in cluster-head to sink node transmission. An analytical method to evaluate the energy consumption based on BER curve is presented. Analysis and simulation results show that proposed cooperative LEACH protocol can save a huge amount of energy over LEACH protocol with same data rate, bit error rate, delay and bandwidth requirements. Moreover, this proposal can achieve higher order diversity with improved spectral efficiency compared to other virtual MIMO based protocols.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.137-141
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• 2007

This paper proposes a cost-effective architecture design of an angle-of-arrival (AOA) estimator based on the multiple signal identification and classification (MUSIC) algerian in UWB systems adapting Multi-band OFDM (MB-OFDM) techniques with two-receive antennas. In the proposed method, by modifying the equations of algorithm in order to remove the high computational functions, the computation power can be significantly reduced without significant performance degradation. The proposed architecture is designed and verified by Verilog HDL, and implemented into 0.13um CMOS standard cell and Xilinx FPGA circuits for the estimation of hardware complexity and computation power. From the results of the implementations, we can find that the proposed circuits reduces the hardware complexity by about 43% and the estimated computation power by about 23%, respectively, compared to the architecture employing the original MUSIC algorithm.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.38 no.10
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• pp.1075-1084
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• 2014

It is necessary to construct an equipment catalog in plant design. A different level of detail may be needed for the three-dimensional (3D) computer aided design (CAD) data for equipment, depending on the purpose. Equipment suppliers provide CAD data with high complexity, whereas plant designers need CAD data with low complexity. Therefore, it is necessary to simplify the 3D CAD assembly data. To resolve this issue, a system for automatically simplifying the 3D CAD assembly data of equipment was developed. This paper presents the architecture of the system, the detailed functions of the system, and a neutral data format used for uploading simplified 3D CAD assembly data to a plant 3D CAD system. In addition, experiment results using the prototype system are explained.

• Journal of IKEEE
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• v.24 no.3
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• pp.783-790
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• 2020

In this paper, the human detecting radar system for indoor security applications is proposed, and its FPGA-based implementation results are presented. In order to minimize the complexity and memory requirements of the computation, the top half of the spectrogram was used to extract features, excluding the feature extraction techniques that require complex computation, feature extraction techniques were proposed considering classification performance and complexity. In addition, memory requirements were minimized by designing a pipeline structure without storing the entire spectrogram. Experiments on human, dog and robot cleaners were conducted for classification, and 96.2% accuracy performance was confirmed. The proposed system was implemented using Verilog-HDL, and we confirmed that a low-area design using 1140 logics and 6.5 Kb of memory was possible.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.2
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• pp.37-43
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• 2008

The performance and hardware complexity of LDPC decoders depend on the design parameters of quantization, the clipping threshold $c_{th}$ and the number of quantization bits q, and also on the maximum number of decoding iterations. In this paper, the BER performances of LDPC codes are evaluated according to the clipping threshold $c_{th}$ and the number of quantization bits q through the simulation studies. By comparing the quantized Min-Sum algorithm with the ideal Min-Sum algorithm, it is shown that the quantized case with $c_{th}=2.5$ and q=6 has the best performance, which approaches the idea case. The decoding complexities are calculated and the word error rates(WER) are estimated by using the pdf which is obtained through the statistical analyses on the iteration numbers. These results can be utilized to tradeoff between the decoding performance and the complexity in LDPC decoder design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7B
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• pp.647-659
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• 2003

LPM(Longest Prefix Matching)searching in If address lookup is a major bottleneck of IP packet processing in the high speed router. In the conventional lookup table for the LPM searching in CAM(Content Addressable Memory) the complexity of fast update take 0(1). In this paper, we designed pipeline architecture for fast update of 0(1) cycle of lookup table and high throughput and low area complexity on LPM searching. Lookup-table architecture was designed by CAM(Content Addressable Memory)away that uses 1bit RAM(Random Access Memory)cell. It has three pipeline stages. Its LPM searching rate is affected by both the number of key field blocks in stage 1 and stage 2, and distribution of matching Point. The RTL(Register Transistor Level) design is carried out using Verilog-HDL. The functional verification is thoroughly done at the gate level using 0.35${\mu}{\textrm}{m}$ CMOS SEC standard cell library.