• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.55-60
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• 2010

For battery-powered device applications, which grow rapidly in the electronic market today, low-power becomes one of the most important design issues of CMOS VLSI circuits. A multi-VDD system, which uses more than one power-supply voltage in the same system, is an effective way to reduce the power consumption without degrading operating speed. However, in the multi-VDD system, level converters should be inserted to prevent a large static current flow for the low-to-high conversion. The insertion of the level converters induces the overheads of power consumption, delay, and area. In this paper, we propose a new level converter which can provide the level up/down conversions for the various input and output voltages. Since the proposed level converter uses only one power-supply voltage, it has an advantage of reducing the complexity in physical design. In addition, the proposed level converter provides lower power and higher speed, compared to existing level converters.

• Proceedings of the KIEE Conference
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• 2001.10a
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• pp.91-93
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• 2001

Linear pulse Motors(LPM) are widely used in fields where smooth linear motion is required, and their position accuracy is higher than other motors. Hybrid linear pulse motors(HLPM) are regarded as an excellent solution to positioning problems that require high accuracy, rapid acceleration and high-speed. The LPM has low mechanical complexity, high reliability, precise open-loop operation and low inertia etc. In many application areas such as factory automation speed positioning, computer peripherals and numerically controlled machine tools, LPM can be used. This motor drive system is especially suitable for machine tools the high position accuracy and repeatability. This paper describes about that need of the embroider machine, we want to design position-scanning device for the embroidery machine. At first, to be analysed characteristics of the machine and next designed the LPM, we used the field analysis program. The finite element method(FEM) program tool is employed for calculation the force. The reluctance models will be used the magnetic permeance of air gap by static-conditions. The forces between forcer and platen have been calculated using the virtual work method. And we used the simulink to know the dynamic characteristics of LPM.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.7
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• pp.413-423
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• 2014

With the increasing demands on high data rate, there has been growing interests in multi-input multi-output (MIMO) technology based on spatial multiplexing (SM) since it can transmit independent information in each spatial stream. Recent standards such as 3GPP LTE-advanced and IEEE 802.11ac support up to eight spatial streams, and massive MIMO and mm-wave systems that are expected to be included in beyond 4G systems are considering employment of tens to hundreds of antennas. Since the complexity of the optimum maximum likelihood based detection method increases exponentially with the number of antennas, low-complexity SM MIMO detection becomes more critical as the number of antenna increases. In this paper, we first review the results on the detection schemes for SM MIMO systems. In addition, massive MIMO reception schemes based on simple linear filtering which does not require exponential increment of complexity will be explained, followed by brief description on receiver design for future high dimensional SM MIMO systems.

• Journal of Communications and Networks
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• v.16 no.4
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• pp.447-457
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• 2014

In this paper, we investigate the frequency domain channel estimation for multiple-input multiple-output (MIMO) single-carrier frequency-division multiple-access (SC-FDMA) systems. In MIMO SC-FDMA, code-division multiplexed (CDM) pilots such as cyclic-shifted Zadoff-Chu sequences have been adopted for channel estimation. However, most frequency domain channel estimation schemes were developed based on frequency-division multiplexing of pilots. We first develop a channel estimation error model by using CDM pilots, and then analyze the mean-square error (MSE) of various minimum MSE (MMSE) frequency domain channel estimation techniques. We show that the cascaded one-dimensional robust MMSE (C1D-RMMSE) technique is complexity-efficient, but it suffers from performance degradation due to the channel correlation mismatch when compared to the two-dimensional MMSE (2D-MMSE) technique. To improve the performance of C1D-RMMSE, we design a robust iterative channel estimation (RITCE) with a frequency replacement (FR) algorithm. After deriving the MSE of iterative channel estimation, we optimize the FR algorithm in terms of the MSE. Then, a low-complexity adaptation method is proposed for practical MIMO SC-FDMA systems, wherein FR is performed according to the reliability of the data estimates. Simulation results show that the proposed RITCE technique effectively improves the performance of C1D-RMMSE, thus providing a better performance-complexity tradeoff than 2D-MMSE.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.3A
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• pp.265-271
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• 2009

This paper proposes an efficient initial frequency estimator for Digital Video Broadcasting-Second Generation (DVB-S2). The initial frequency offset of the DVB-S2 is around ${\pm}5MHz$, which corresponds to 20% of the symbol rate at 25Msps. To estimate a large initial frequency offset, the algorithm which call provide a large estimation range is required. Through the analysis of the data-aided (DA) algorithms, we find that the Mengali and Moreli (M&M) algorithm can estimate a large initial frequency offset at low SNR. Since the existing frequency estimator based on M&M algorithm has a high hardware complexity, we propose the methods to reduce the hardware complexity of the initial frequency estimator. This can be achieved by reducing the number of autocorrelators and arctangents. The proposed architecture can reduce the hardware complexity about 64.5% compared to the existing frequency estimator and has been thoroughly verified on the Xilinx Virtex II FPGA board.

• Proceedings of the Korean Geotechical Society Conference
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• 2004.03b
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• pp.938-945
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• 2004

In order to cope with ever growing traffic flow and complexity in the urban area, construction demands for expanding and realigning of existing urban roads and massive development of underground space within the urban area are in its increasing trend, it is fact that, mainly due to lack of statistical data accumulation through real construction, technology and construction practice to support such demands can hardly be said to have been established enough and leave many things still to be developed. These circumstances therefore came to motivate me to get into a study for a particular subject of "Design Basics for Closely Neighbored Twin Tunnel" among others, and also to put forward subjects required to be further studied in this connection in the future as follows: 1) To make a new economical design model for closely neighbored twin tunnel not only to make a drain for center perfect but also a tunnel construction safe. 2) Further efforts should be exerted for establishment of general standards for design and construction of various types of large cross-section tunnels including Twin structure.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.6
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• pp.477-487
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• 2005

As embedded system grows in size and complexity, the importance of the technique for dynamic memory allocation has increased. The objective of this paper is to measure the performance of dynamic memory allocation by varying both hardware and software design parameters for embedded systems. Unlike torrent performance evaluation studies that have presumed the single threaded system with single address spate without OS support, our study adopts realistic environment where the embedded system runs on Linux OS. This paper contains the experimental performance analyses of dynamic memory allocation method by investigating the effects of each software layer and some hardware design parameters. Our quantitative results tan be used to help system designers design high performance, low power embedded systems.

• The KIPS Transactions:PartD
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• v.15D no.2
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• pp.213-222
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• 2008

The existing approaches for the music application have not considered a real-time multi-tasking model. So, it suffers from a high complexity and a low flexibility in design as well as lack of predictability for the timely execution of critical tasks. In this paper, we design a new concurrent tasking architecture for a real-time embedded music system and examine if all real-time tasks can finish execution within their respective time constraints. The design is implemented on the Linux based Xhyper272 Board that uses the Intel Bulverde microprocessor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.6
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• pp.689-697
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• 2016

In this paper, we design and implement SPA (Switched Parasitic Antenna) antenna which can control its beampattern using multiple parasitic elements. By applying SPA antenna to wireless communication system and implementing beamforming scheme, we show that SPA antenna can be used to improve the performance of wireless communication systems. SPA antenna consists of a single active antenna and multiple parasitic elements around the active one, and can control its beampattern by switching the parasitic elements. Using this characteristic of the SPA antenna, it is possible to impelemtent beamforming technique with single RF chain, which enables to design low cost, low complexity and low power wireless communication systems. In order to verify the beamforming gain, we measure and analyze the system level performance, such as SNR, PER, and throughput.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.61-68
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• 2005

A chip, which can fast encoder the audio data to AAC (Advanced Audio Coding) LC(Low Complexity) that is MPEG-2 audio standard, has been designed on the basis of a 32 bits DSP core and fabricated with 0.25um CMOS technology. At first, the various optimization methods for implementing the algerian are devised to reduce the memory size and calculation cycles. FFT(Fast Fourier Transform) hardware block is added to the DSP core to get the more reduction of the calculation cycles. The chips has the size of $7.20\times7.20 mm^2$ and about 830,000 equivalent gates, can carry out AAC encoding under 70MIPS(Million Instructions per Second).