• Title/Summary/Keyword: low power network

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AI Processor Technology Trends (인공지능 프로세서 기술 동향)

  • Kwon, Youngsu
    • Electronics and Telecommunications Trends
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    • v.33 no.5
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    • pp.121-134
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    • 2018
  • The Von Neumann based architecture of the modern computer has dominated the computing industry for the past 50 years, sparking the digital revolution and propelling us into today's information age. Recent research focus and market trends have shown significant effort toward the advancement and application of artificial intelligence technologies. Although artificial intelligence has been studied for decades since the Turing machine was first introduced, the field has recently emerged into the spotlight thanks to remarkable milestones such as AlexNet-CNN and Alpha-Go, whose neural-network based deep learning methods have achieved a ground-breaking performance superior to existing recognition, classification, and decision algorithms. Unprecedented results in a wide variety of applications (drones, autonomous driving, robots, stock markets, computer vision, voice, and so on) have signaled the beginning of a golden age for artificial intelligence after 40 years of relative dormancy. Algorithmic research continues to progress at a breath-taking pace as evidenced by the rate of new neural networks being announced. However, traditional Von Neumann based architectures have proven to be inadequate in terms of computation power, and inherently inefficient in their processing of vastly parallel computations, which is a characteristic of deep neural networks. Consequently, global conglomerates such as Intel, Huawei, and Google, as well as large domestic corporations and fabless companies are developing dedicated semiconductor chips customized for artificial intelligence computations. The AI Processor Research Laboratory at ETRI is focusing on the research and development of super low-power AI processor chips. In this article, we present the current trends in computation platform, parallel processing, AI processor, and super-threaded AI processor research being conducted at ETRI.

A CMOS Frequency divider for 2.4/5GHz WLAN Applications with a Simplified Structure

  • Yu, Q.;Liu, Y.;Yu, X.P.;Lim, W.M.;Yang, F.;Zhang, X.L.;Peng, Y.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.11 no.4
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    • pp.329-335
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    • 2011
  • In this paper, a dual-band integer-N frequency divider is proposed for 2.4/5.2 GHz multi-standard wireless local area networks. It consists of a multi-modulus imbalance phase switching prescaler and two all-stage programmable counters. It is able to provide dual-band operation with high resolution while maintaining a low power consumption. This frequency divider is integrated with a 5 GHz VCO for multi-standard applications. Measurement results show that the VCO with frequency divider can work at 5.2 GHz with a total power consumption of 22 mW.

New Single-stage Interleaved Totem-pole AC-DC Converter for Bidirectional On-board Charger

  • ;Kim, Sang-Jin;Kim, Byeong-U;Sin, Yang-Jin;Choe, Se-Wan
    • Proceedings of the KIPE Conference
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    • 2018.07a
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    • pp.192-194
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    • 2018
  • In this paper a new single-stage ac-dc converter with high frequency isolation and low components count is introduced. The proposed converter is constructed using two interleaved boost circuits in the grid side and non-regulating full bridge in the DC side. An optimized switching is implemented on the two interleaved boost circuits resulting in a ripple-free grid current without a ripple cancellation network; hence very small filter inductors are used. A simple and reliable closed-loop control system is easily implemented, since the phase-shift angle is the only independent variable. Moreover, current imbalance is avoided in the presented topology without current control loop in each phase. The proposed charger charges the battery with a sinusoidal-like current instead of a constant direct current. ZVS turn on of all switches is achieved throughout the operation in both directions of power flow without any additional components.

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Measurements of the Ground Resistance using the Test Current Transition Method in Powered Grounding Systems (측정전류전이법을 이용한 운전중인 접지시스템의 접지저항 측정)

  • Lee, Bok-Hui;Eom, Ju-Hong;Kim, Seong-Won
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.51 no.8
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    • pp.347-353
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    • 2002
  • This paper presents an accurate method for measuring the ground resistance in powered grounding system. Most of substations and electric power equipments are interconnected to an extensive grounding network of overhead ground wires, neutral conductors of transmission lines, cable shields, and etc. The parasitic effects due to circulating ground currents and ground potential rise make a significant error in measuring the ground resistance. The test current transition method was proposed to reduce the effects of stray ground currents, ground potential rise and harmonic components in measurements of the ground resistance for powered grounding systems. The instrumental error of the test current transition method is decreased as the ratio of the test current signal to noise(S/N) increases. It was found from the test results that the proposed measuring method of the ground resistance is more accurate than the conventional fall-of-potential method or low-pass filter method, and the measuring error was less than 3[%]when S/N is 10.

Experimental deployment and validation of a distributed SHM system using wireless sensor networks

  • Castaneda, Nestor E.;Dyke, Shirley;Lu, Chenyang;Sun, Fei;Hackmann, Greg
    • Structural Engineering and Mechanics
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    • v.32 no.6
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    • pp.787-809
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    • 2009
  • Recent interest in the use of wireless sensor networks for structural health monitoring (SHM) is mainly due to their low implementation costs and potential to measure the responses of a structure at unprecedented spatial resolution. Approaches capable of detecting damage using distributed processing must be developed in parallel with this technology to significantly reduce the power consumption and communication bandwidth requirements of the sensor platforms. In this investigation, a damage detection system based on a distributed processing approach is proposed and experimentally validated using a wireless sensor network deployed on two laboratory structures. In this distributed approach, on-board processing capabilities of the wireless sensor are exploited to significantly reduce the communication load and power consumption. The Damage Location Assurance Criterion (DLAC) is used for localizing damage. Processing of the raw data is conducted at the sensor level, and a reduced data set is transmitted to the base station for decision-making. The results indicate that this distributed implementation can be used to successfully detect and localize regions of damage in a structure. To further support the experimental results obtained, the capabilities of the proposed system were tested through a series of numerical simulations with an expanded set of damage scenarios.

Double-tuned Filter Design For HVDC System (HVDC System 적용 Double-tuned 필터의 설계 방법 연구)

  • Lee, Hee-Jin;Nam, Tae-Sik;Son, Gum-Tae;Park, Jung-Wook;Chung, Yong-Ho;Lee, Uk-Hwa;Baek, Seung-Taek;Hur, Kyeon
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.61 no.9
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    • pp.1232-1241
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    • 2012
  • The ac side current of an high voltage direct current (HVDC) converter is characterized by highly non-sinusoidal waveform. If the harmonic current is allowed to flow in the connected ac system, it may cause unacceptable levels of distortion. Therefore, ac side filters are required as part of the total HVDC converter station, in order to reduce the harmonic distortion of the ac side current and voltage to acceptably low levels. The ac side filters are also employed to compensate network requested reactive power because HVDC converters also consume substantial reactive power. Among different types of filters, double-tuned filters have been widely utilized for HVDC system. This paper presents two design methods of double-tuned filter; equivalent method and parametric method. Using a parametric method, in particular the paper proposes a new design algorithm for a realistic system. Finally, the performance of the design algorithm is evaluated for a 80kV HVDC system in Jeju island with PSCAD/EMTDC program. The results cleary demonstrate the effectiveness of proposed design method in harmonics elimination and steady-state stability.

A Reassessment for Dynamic Line Rating of Aged Overhead Transmission Lines in Kepco's Network (한국전력 노후 가공송전선의 동적송전용량에 대한 재평가)

  • Kim, Sung-Duck
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.24 no.10
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    • pp.123-129
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    • 2010
  • During the past 2 decades, many electric power companies have been searching various solutions in order to supply power with economical and more efficiency in the present transmission utilities. Most interesting method to increase the line capacity of overhead transmission lines without constructing any new line might be to adapt Dynamic Line Rating(DLR). Specified rating is normally determined by any current level, not by conductor temperature. Although specified rating is essential to design transmission line, dip may be the most important factor in limiting transmission capacity. Transmission lines built by the oldest dip criterion among the 3 different design criteria for conductor dip are nearly over one-half of all Kepco's transmission lines. This paper describes an up-rating method for those transmission lines in order to apply DLR technique. Based on limit dip conductor temperature and current of the transmission lines, limitation performance and effectiveness in applying DLR with weather model are analyzed. As a result of analysis, it can be shown that an improved method could be effectively used for increasing the line rating of old transmission line which was built by the design criterion with low dip margin.

The performance analysis of Reflective Semiconductor Optical Amplifier Modulator in WDM-PON system (파장분할다중 광가입자망을 위한 반사형 반도체 광증폭기 변조 성능 분석)

  • Shim Woo-Jin;Shin Yong-Sik;Park Yong-Gil
    • Journal of The Institute of Information and Telecommunication Facilities Engineering
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    • v.4 no.1
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    • pp.15-21
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    • 2005
  • One of the core technology in WDM-PON system is a generation and modulation technique of the optical source in Optical Network Unit (ONU). In this paper, we propose a reflective semiconductor optical amplifier (RSOA) as a modulator in WDM-PON system. Its performance is analyzed by simulation and actual experimentation. Using RSOA in WDM-PON system as a modulator, it obtains higher gain compared to the conventional SOA due to the double pass gain effect. Furthermore RSOA can provide high gain with comparatively low input power. This is very helpful when we set up the actually system because using lower input power, it can reduce the load of the driving circuit which makes very economical module structure. Therefore, when RSOA is used as a modulator, not only it gives noise suppression effect, but also provides certain amount of gain as well. In addition, comparing with conventional SOA which gives fairly large insertion loss, RSOA can provides more important merits.

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A study for Network Performance of Power-Line Communication Using Low Voltage Power-Line (저압 전력선을 이용한 전력선 통신망의 네트워크 성능에 관한 연구)

  • Kwon, Soon-Won;Cho, Sung-Bae;Oh, Hui-Myoung;Lee, Jae-Jo;Kim, Kwan-Ho;Hong, Choong-Seon
    • Proceedings of the KIEE Conference
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    • 2003.07d
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    • pp.2699-2701
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    • 2003
  • 전력선 통신 기술의 발달에 따라 다양한 전력선 통신 핵심 기술들이 적용된 모뎀이 개발되고 있는 시점에서, 상용화에 앞서 모뎀 성능에 대한 실제적인 측정과 검토가 요구된다. 본 논문에서는 저압 전력선(옥내) 통신 테스트 베드를 구성, 이를 통해 모뎀의 네트워크 성능 지표들에 대한 실제적인 측정을 수행하였다. 저압 전력선은 220V저압에 옥내 배전선 약 16m로 구성되었으며, 측정된 네트워크 성능 지표는 RFC2544, RFC2285에서 권고하는 네트워크 성능 지표들 중, 일대일 처리율, 일대다 처리율, 다대일 처리율, 일대일 지연시간, 일대일 프레임 손실이다. 측정에 사용된 전력선 모뎀의 성능과 지표들의 측정값을 통해 모뎀의 성능과 속도뿐만 아니라 전력선 통신 어플리케이션 적용 여부 등 전력선 통신 시스템 개발과 상용화에 실제적인 검토가 가능하다.

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Low cost optical add/drop module for WDM optical transmission systems (WDM 기반의 광통신망을 위한 저가형 광신호 삽입/추출 모듈)

  • 조승현;박재동;정의석;김병휘;강민호;신동욱
    • Korean Journal of Optics and Photonics
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    • v.14 no.6
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    • pp.578-582
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    • 2003
  • We propose a novel structure of wavelength selective optical add/drop module comprising two tap couplers and a fiber Bragg grating. The device has unique features including a simpler structure and a lower cost of implementation as compared with existing devices for the same operation. The module performance has been measured and analyzed experimentally. The implemented prototype module shows good performance with no-crosstalk power penalty in a 155 Mbps per channel wavelength-division-multiplexing transmission system but suffers from a relatively high loss of 3.5 ㏈ and 21 ㏈ for transmitted and dropped channels, respectively. While the dropped channel extinction ratio was more than 25 ㏈, the transmitted channel extinction ratio was more than 35 ㏈.