• Electronics and Telecommunications Trends
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• v.33 no.6
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• pp.24-33
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• 2018

In the age of IoT, in which everything is connected to a network, there have been increases in the amount of data traffic, latency, and the risk of personal privacy breaches that conventional cloud computing technology cannot cope with. The idea of edge computing has emerged as a solution to these issues, and furthermore, the concept of ultra-low power edge intelligent semiconductors in which the IoT device itself performs intelligent decisions and processes data has been established. The key elements of this function are an intelligent semiconductor based on artificial intelligence, connectivity for the efficient connection of neurons and synapses, and a large-scale spiking neural network simulation framework for the performance prediction of a neural network. This paper covers the current trends in ultra-low power edge intelligent semiconductors including issues regarding their technology and application.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.777-780
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• 2014

The sensor network technology for core technology of ubiquitous computing is in the spotlight recently, the research on sensor network is proceeding actively which is composed many different sensor node. The major traffic patterns of plenty of sensor networks are composed of collecting types of single directional data, which is transmitting packets from several sensor nodes to sink node. One of the important condition for design of sensor node is to extend for network life which is to minimize power-consumption under the limited resources of sensor network. In this work, we analysis adapted routing protocols using the network simulation that was used exiting network and network provider needs will be able to solve the problem.

• Journal of Information Technology Services
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• v.14 no.1
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• pp.159-173
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• 2015

This paper presents a study on the Internet of Things based low-power wireless sensor networks for remote monitoring of wildlife ecosystem due to climate change. Especially, it is targeting the wild vegetation communities ecological monitoring. First, we performed a pre-test and analysis for selecting the appropriate frequency for the sensor network to collect and deliver information reliably in harsh propagation environment of the forest area, and selected for sensors for monitoring wild vegetation communities on the basis of considerations for selecting the best sensor. In addition, we have presented the platform concept and hierarchical function structures for effectively monitoring, analyzing and predicting of ecosystem changes, to apply the Internet of Things in the ecological monitoring area. Based on this, this paper presents the system architecture and design of the Internet of Things based low-power wireless sensor networks for monitoring the ecosystem of the wild vegetation communities. Finally, we constructed and operated the test-bed applied to real wild trees, using the developed prototype based on the design.

• Journal of Communications and Networks
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• v.15 no.3
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• pp.292-300
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• 2013

Nowadays, energy saving has become a hot topic and information and communication technology has become a major power consumer. In long term evolution advanced (LTE-A) networks, heterogeneous deployments of low-power nodes and conventional macrocells provide some new features, such as coverage extension, throughput enhancement, and load balancing. However, a large-scale deployment of low-power nodes brings substantial energy consumption and interference problems. In this paper, we propose a novel switching strategy (NS), which adaptively switches on or off some low-power nodes based on the instantaneous load of the system. It is compatible with the microcells' load balancing feature and can be easily implemented on the basis of existing LTE-A specifications. Moreover, we develop an analytical model for analyzing the performance of system energy consumption, block rate, throughput, and energy efficiency. The performance of NS is evaluated by comparison with existing strategies. Theoretical analysis and simulation results show that NS not only has a low block rate, but also achieves a high energy efficiency.

• Journal of Sensor Science and Technology
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• v.29 no.1
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• pp.68-73
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• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.9
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• pp.1367-1373
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• 2022

In this paper, we consider a power re-allocation technique in order to enhance the frequency efficiency of the low performance user in a cell-free multiple input multiple output (MIMO) network. The AP first allocates transmit power to the user to be proportional to the large-scale fading coefficients of the connected users. Then, the AP reduces the power of the users who were allocated power greater than the threshold ratio of total allocated power to be equal to the threshold ratio of the allocated power. Finally, the AP re-allocates the reduced power from the strong channel user to the user who has the worst channel condition, and thus, the frequency efficiency of the low performance user can be enhanced. In the simulation results, we verify the performance of the power re-allocation technique in terms of the spectral efficiency of the low performance user.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.451-453
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• 2007

This paper describes the design of an asynchronous implementation of a sensor network processor. The main purpose of this work is the reduction of power consumption in sensor network node processors and the research presented here tries to explore the suitability of asynchronous circuits for this purpose. The Handshake Solutions toolkit is used to implement an asynchronous version of a sensor processor. The design is made compact, trading area and leakage power savings with dynamic power costs, targeting the typical sparse operating characteristics of sensor node processors. It is then compared with a synchronous version of the same processor. Both versions are then compared with existing commercial processors in terms of power consumption.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.731-734
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• 2011

This paper proposed the Low power configuration of Single hop WSN(Wireless Sensor Network) system. When the RF communication is done each tag node during the WSN systems operating, power consumption is greatest. There for, if you configure the Network with the RF communication module turn on/off periodically, power consumption less then operating the module all the time without it toggles. However, some data omissions may occur in which transmission and receipt is done. So this paper proposed the algorithm for low power system without data omissions.

• ETRI Journal
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• v.24 no.6
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• pp.473-476
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• 2002

This letter proposes an efficient kernel-based partitioning algorithm for reducing area and power dissipation in combinational circuit designs using don't-care sets. The proposed algorithm decreases power dissipation by partitioning a given circuit using a kernel extracted from the logic. The proposed algorithm also reduces the area overhead by minimizing duplicated gates in the partitioned sub-circuits. The partitioned subcircuits are further optimized utilizing observability don't-care sets. Experimental results for the MCNC benchmarks show that the proposed algorithm synthesizes circuits that on the average consume 22.5% less power and have 12.7% less area than circuits generated by previous algorithms based on a precomputation scheme.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.5
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• pp.197-202
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• 2002

In this paper, the characteristics of the household AC power line network is analyzed for the low bit rate powerline communication (PLC) in the frequency range from 10㎑ to 450㎑ The PLC channel transfer characteristics including its characteristic impedance are derived based on the network topology which is constructed with the household power lines loaded with the various types of electric apparatus. Both the distributed circuit analysis and the lumped circuit model based analysis are applied for the characterization of the PLC channel and the results are compared by the computer simulations. The analysis illustrates very well the adverse effects caused by the loading of electric apparatus and as well those casued by the reflection of wavers in the household AC Power line communication network.