• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.12 s.91
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• pp.1184-1189
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• 2004

A new schematic of quadrature voltage controlled oscillator(QVCO) is designed and fabricated. To obtain quadrature characteristic and low phase noise simultaneously, two differential VCOs are forced to un in quadrature mode by using coupling amplifier with a source degeneration resistor, which is optimized to obtain quadrature accuracy with minimum phase noise degradation. The designed QVCO was fabricated in standard CMOS technology. The measured performance showed the phase noise of below -120 dBc/Hz at 1 MHEz frequency offset, tuning bandwidth of 210 MHz from 2.34 GHz to 2.55 GHz with a tuning voltage varying form 0 to 1.8 V Quadrature error of 0.5 degree and amplitude error of 0.2 dB was measured with conjunction with low-lF mixer. The fabricated QVCO requires 19 mA including 5 mA in the VCO core part fiom a 1.8 V supply.

• The Journal of the Acoustical Society of Korea
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• v.27 no.1
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• pp.1-11
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• 2008

To overcome the mid frequency limitation of geometrical acoustic techniques, the phased geometrical method was suggested by introducing the phase information into the sound propagation from the source. By virtue of phase information, the phased tracing method has a definite benefit in taking the interference phenomenon at mid frequencies into account. Still, this analysis technique has suffered from difficulties in dealing with low frequency phenomena, so called, wave nature of sound. At low frequencies, diffraction at corners, edges, and obstacles can cause errors in simulating the transfer function and the impulse response. Due to the use of real valued absorption coefficient, simulated results have shown a discrepancy with measured data. Thus, incorrect phase of the reflection characteristic of a wall should be corrected. In this work, the uniform theory of diffraction was integrated into the phased beam tracing method (PBTM) and the result was compared to the ordinary PBTM. By changing the phase of the reflection coefficient, effects of phase information were investigated. Incorporating such error compensation methods, the acoustic prediction by PBTM can be further extended to low frequency range with improved accuracy in the room acoustic field.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.12a
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• pp.117-121
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• 2003

In this paper, a micromachined low-loss and ultra wide band reflection-type phase shifter (RTPS) is proposed. The phase shifter shows a constant phase shift from 5 to 17 GHz and consists of two cascaded reflection-type phase shifter. Low-loss reflection termination consists of digital capacitive switches, and air-gap overlay CPW couplers are used in order to employ the low-loss 3 dB coupling. The fabricated phase shifter showed the 5 discrete states, $0^{\circ},{\;}22.5^{\circ},{\;}45^{\circ},{\;}67.5^{\circ},{\;}90^{\circ}$ respectively, the average insertion loss of 3.48 dB, and maximum rms phase error of ${\pm}1.80^{\circ}$ for the relative phase shift from $0^{\circ}{\;}to{\;}90^{\circ}$ over 5-17 GHz.

• Journal of Navigation and Port Research
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• v.36 no.8
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• pp.631-635
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• 2012

Underwater acoustic communication has multipath error because of reflection by sea-level and sea-bottom. The multipath of underwater channel causes signal distortion and error floor. In this paper, in order to design an efficient packet structure, we employ channel coding scheme and phase recovery algorithm. For channel coding scheme, half rate LDPC channel coding scheme with N=1944 and K=972 was used. Also, decision directed phase recovery was used for correcting phase offset induced by multipath. Based on these algorithms, we propose length of data for optimal packet structure in the environment of oceanic experimentation.

• Proceedings of the KIPE Conference
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• 2008.10a
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• pp.124-126
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• 2008

Grid Connected inverter is produced current to deliver power to grid. To provide low THD current, LCL filters is effective to filter high frequency component of current output from inverter. To provide sinusoidal waveform, there are many researchers have been proposed several controllers for grid-connected inverter controllers. Synchronous Reference Frame (SRF)-based controller is the most popular methods. SRF-based controller is capable for reducing both of zero-steady state error and phase delay. But SRF based controller is contained cross-coupling components, which generate some difficulties to analyze. In this paper, SRF based controller is analyzed. By applying decoupling control, cross-coupling component is eliminated and single phase model of the system is obtained. Through this single phase model, gain controller is designed. To reduce steady state error, proportional gain is set as high as possible, but it may produce instability. To compromise between a minimum steady state error and stability, the single phase model is evaluate through Root Locus and Bode diagram. PSIM simulation is used to verify the analysis.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.2
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• pp.96-104
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• 2009

This paper proposes a single-phase Phase-locked loop (PLL) of the virtual two phase generator using full-order state observer, which is essential to find phase and frequency of the single-phase source. The conventional methods cannot remove the low-order harmonics included in source voltage, which influencesto whole PLL control system. The proposed algorithm separates fundamental wave from harmonics, and removes harmonics effectively. Therefore it generates only the fundamental wave. As it controls virtual voltage and input voltage together, it decreases steady-state error. From simulation and experimental results, the generated frequency by the proposed PLL which it plans, converges to the actual value, and the steady-state error is much reduced under given harmonic voltages. It is also confirmed that the proposed algorithm removed harmonics effectively and it generates only the fundamental wave.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.1
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• pp.35-41
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• 2014

This paper presents a design method of programmable low pass filter(PLPF) which reduce an estimation error of a zero crossing point(ZCP) for a high speed brushless DC(BLDC) motor drive. BLDC motor sensorless drive is possible by estimation of ZCP. The ZCP estimated by detecting a change of back-EMF polarity has the estimation error because noises exist on the measured back-EMF. Therefore a calculated commutation timing using the ZCP is inaccurate. And the inexact commutation timing leads to ripples of 3-phase current and degradation of drive performance. This paper proposes the design method of the PLPF to overcome these problems. First, a speed calculated a inaccurate period of the ZCP is analyzed in the frequency domain. Then, the PLPF that has varying cut-off frequency according to change of the speed is designed on the frequency analysis result. The proposed method is verified by the experiment.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2075-2077
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• 2001

For precise positioning, GPS carrier measurements are often used. In this case, accurate position having mm${\sim}$cm error can be obtained. For 3D positioning, in CDGPS, more than five carrier phase measurements are required. When GPS signals are blocked or carrier phase measurements are insufficient, it cannot provide positioning solution. By integrating CDGPS with INS, continuity of positioning solution can be guaranteed. However, when a vehicle moves in low speed or in stationary, the CDGPS/INS integrated system is difficult to compensate INS attitude errors because GPS velocity error become relatively lange. In this paper, we used the 3D attitude GPS receiver to compensate the INS attitude error. By field experiments, it is shown that the proposed integration system maintains the navigation performance even when a vehicle is in low speed or GPS signal is blocked for a period of time.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3097-3099
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• 2000

In this paper, we design PLL for a low jitter and fast locking time that is used a new simple precharged CMOS phase frequency detector(PFD). The proposed PFD has a simple structure with using only 18 transistors. Futhermore, the PFD has a dead zone 25ps in the phase characteristic which is important in low jitter applications. The phase and frequency error detection range is not limited as the case of other precharge type PFDs. the simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD. the PLL using the new PED is designed using 0.25${\mu}m$ CMOS technology with 2.5V supply voltage.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.10
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• pp.708-711
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• 2000

Sensorless PMSM is much studied for the industrial applications and home appliances because a mechanical sensor reduce reliability and increase cost. Most of sensorless algorithms are based on motor equations, and so the magnitude of phase voltage and current should be exactly obtained. However, the inverter output voltage applied to PMSM has relatively large error in the low speed range, and a relatively poor response is shown in the low speed range. This paper investigates the improved performance of sensorless PMSM in the low speed range. This paper proposes the error reduction of inverter output voltage which is realized through the variable link voltage. The proposed algorithm is verified through simulation and experiment.