• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.6 no.6
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• pp.32-41
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• 1992

In this paper, an advanced Pulse Width Modulation Inverter strategy for driving a variable-speed induction motor is introduced. A switching pattern making use of the near-proportionality of voltage and frequency in AC machines operating with constant flux was computed. At low magnitudes and ow frequencies of the fundamental, many more harmonics are eliminated than at high magnitudes and frequencies. In order to keep the inverter switching frequency constant over the output frequency range, the chopping frequency is diminished as the frequency of the fundamental increases. Using these modulation strategy, the harmonics components of PWM inverter are efficiently eliminated.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1650-1658
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• 2018

Multilevel converters are being widely used in medium-voltage high-power applications including motor drive systems, utility power transmission, and distribution systems. Selective harmonic elimination (SHE) is a well-known modulation method to generate high quality output voltage waveforms. This paper presents a new simple practical method for generating a generalized five-level waveform without selected low order harmonics. This method is based on a phase-shifted expression for the SHE problem, which can analytically calculate the exact values of switching angles and the feasible modulation index range for three-level and five-level waveforms. The proposed method automatically determines the number of transitions between levels and generates proper output waveform without solving complex trigonometric equations. Due to the simplicity of the computational burden, the real-time implementation of the proposed algorithm can be performed by a simple processor. Simulation and experiment results verify the correctness and effectiveness of the proposed method.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.600-604
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• 1991

In this paper, an advanced PWM modulation strategy for driving a variable-speed induction motor is introduced. According to this method, the technique of efficiently eliminating harmonics component is achived. A switching pattern was computed making use of the near-proportionality of voltage and frequency in AC machines operating with constant flux. At low magnitudes and low frequencies of the foundamental, many more harmonics are eliminated than at high magnitudes and frequencies. In order to keep the inverter switching frequency constant over the output frequency range, chopping times diminishes as the frequency of the fundamental increases.

• Advances in nano research
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• v.3 no.1
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• pp.49-54
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• 2015

The structure represents symmetrical metal electrode (gate 1) - front $SiO_2$ layer - n-Si nanowire FET - buried $SiO_2$ layer - metal electrode (gate 2). At the symmetrical gate voltages high conductive regions near the gate 1 - front $SiO_2$ and gate 2 - buried $SiO_2$ interfaces correspondingly, and low conductive region in the central region of the NW are formed. Possibilities of applications of nanosize FETs at the deep inversion and depletion as a distributed capacitance are demonstrated. Capacity density is an order to ${\sim}{\mu}F/cm^2$. The charge density, it distribution and capacity value in the nanowire can be controlled by a small changes in the gate voltages. at the non-symmetrical gate voltages high conductive regions will move to corresponding interfaces and low conductive region will modulate non-symmetrically. In this case source-drain current of the FET will redistributed and change current way. This gives opportunity to investigate surface and bulk transport processes in the nanosize inversion channel.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.170-183
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• 2013

This paper gives an overview of fractional-N phase-locked loops (PLLs) with practical design perspectives focusing on a ${\Delta}{\Sigma}$ modulation technique and a finite-impulse response (FIR) filtering method. Spur generation and nonlinearity issues in the ${\Delta}{\Sigma}$ fractional-N PLLs are discussed with simulation and hardware results. High-order ${\Delta}{\Sigma}$ modulation with FIR-embedded filtering is considered for low noise frequency generation. Also, various architectures of finite-modulo fractional-N PLLs are reviewed for alternative low cost design, and the FIR filtering technique is shown to be useful for spur reduction in the finite-modulo fractional-N PLL design.

• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.378-380
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• 1996

This paper presents the novel control and analysis of GTO-CSC. The control method is based on the linearization of an optimal modulation strategy so that the turn-on-periods of the GTO switches can be computed in real-time for any specified modulation index. These PWM patterns allow to produce minimal ac line current low order harmonics of ac line current and low switchings. Finally, the computer simulation results are presented to verify the theoretical analysis.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1306-1315
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• 2016

Modern power systems driven by high-power converters have become inevitable in view of the ever increasing demand for electric power. The total power loss can be reduced by limiting the switching losses in such power converters; increased power efficiency can thus be achieved. A reduced switching frequency that is less than a few hundreds of hertz is applied to power converters that produce output waveforms with high distortion. Selective harmonic elimination pulse width modulation (SHEPWM) is an optimized low switching frequency pulse width modulation method that is based on offline estimation. This method can pre-program the harmonic profile of the output waveform over a range of modulation indices to eliminate low-order harmonics. In this paper, a SHEPWM scheme for three-phase three-leg neutral point clamped inverter is proposed. Aside from eliminating the selected harmonics, the DC capacitor voltages at the DC bus are also balanced because of the symmetrical pulse pattern over a quarter cycle of the period. The technique utilized in the estimation of switching angles involves the firefly algorithm (FA). Compared with other techniques, FA is more robust and entails less computation time. Simulation in the MATLAB/SIMULINK environment and experimental verification in the very large scale integration platform with Spartan 6A DSP are performed to prove the validity of the proposed technique.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.50 no.10
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• pp.513-519
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• 2001

This paper proposed a random sigma-delta modulator(RSDM), which is constructed by a 1st order sigma-delta modulator(SDM) and a simple structured random binary generator(RBG). The 1st order SDM produces a switching pulse waveform which has the same low-frequency component as the reference input, while the RBG spreads the distribution of the number of sampling per switching cycle, and thus disperses the spectrum spikes in the output. The relationship between the harmonic spectra and the number of sampling per switching cycle is studied through computer simulations, and the frequency spectra of the RSDM are confirmed in an experimental setup.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.160-167
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• 1996

A new pathlength deviation detection technique which is composed of michelson interferometer is described and verified experimentally. The technique uses a sub-threshold biased visible laser diode of 20$\mu$m coherence length as a low-coherent light source. And for zeroth-order fringe(which is the largest among fringes) identification we used a piezoelectric transducer with a large modulation smplitude, which enables without the need of constant velocity scanning, to distinguish reflection surfaces separated by more than 10$\mu$m with a resolution of less than half-wavelength.

• Journal of Power Electronics
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• v.16 no.2
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• pp.512-521
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• 2016

Cascaded H-bridge multilevel (CHBML) inverters usually include a large number of isolated dc-voltage sources. Some faults in the dc-voltage sources result in unequal cell dc voltages. Unfortunately, the conventional phase-shifted carrier (PSC) PWM method that is widely used for CHBML inverters cannot eliminate low frequency sideband harmonics when the cell dc voltages are not equal. This paper analyzes the principle of sideband harmonic elimination, and proposes an improved PSCPWM that can eliminate low frequency sideband harmonics under the condition of unequal dc voltages. In order to calculate the carrier phases, it is necessary to solve transcendental equations for low frequency sideband harmonic elimination. Therefore, an approach based on the artificial bee colony (ABC) algorithm is presented in this paper. The proposed PSCPWM method enhances the reliability of CHBML inverters. The proposed PSCPWM is not limited to CHBML inverters. It can also be applied to other types of multilevel inverters. Simulation and experimental result obtained from a prototype CHBML inverter verify the theoretical analysis and the achievements made in this paper.