• Journal of Power Electronics
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• v.16 no.3
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• pp.960-969
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• 2016

High-power three-level voltage-source converters are widely utilized in high-performance AC drive systems. In several ultra-power instances, the harmonics on the grid side should be reduced through multiple rectifications. A combined harmonic elimination method that includes a dual primary-side series-connected winding transformer and selective harmonic elimination pulse-width modulation is proposed to eliminate low-order current harmonics on the primary and secondary sides of transformers. Through an analysis of the harmonic influence caused by dead time and DC magnetic bias, a synthetic compensation control strategy is presented to minimize the grid-side harmonics in the dual primary side series-connected winding transformer application. Both simulation and experimental results demonstrate that the proposed control strategy can significantly reduce the converter input current harmonics and eliminates the DC magnetic bias in the transformer.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.9
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• pp.2456-2469
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• 1996

A digital satellite communication channel has a nonlinearity with memory due to saturation characeristis of the high poer amplifier in the satellite and transmitter/receiver linear filter used in the overall system. In this paper, we propose a complex radial basis function network(CRBFN) based adaptive equalizer for compensation of nonlinearities in digital satellite communication channels. The proposed CRBFN untilizes a complex-valued hybrid learning algorithm of k-means clustering and LMS(least mean sequare) algorithm that is an extension of Moody Darken's algorithm for real-valued data. We evaluate performance of CRBFN in terms of symbol error rates and mean squared errors nder various noise conditions for 4-PSK(phase shift keying) digital modulation schemes and compare with those of comples pth order inverse adaptive Volterra filter. The computer simulation results show that the proposed CRBFN ehibits good equalization, low computational complexity and fast learning capabilities.

• Journal of Power Electronics
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• v.19 no.5
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• pp.1182-1192
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• 2019

In order to improve the conversion efficiency and mitigate the EMI problem of conventional hard-switching inverters, a new soft-switching DC-AC inverter with a compact structure and a low modulation complexity is proposed in this paper. In the proposed structure, resonant inductors are connected in series for the arm branches, and resonant capacitors are connected in parallel for the neutral point branches. With the help of resonant components, the proposed structure achieves zero-current switching on the arm branches and zero-voltage switching on the neutral point branches. When compared with state-of-art soft-switching topologies, the proposed topology does not need auxiliary switches. Moreover, the commutation algorithm to realize soft-switching can be easily implemented. In this paper, the principle of the resonant operation of the proposed soft-switching converter is presented and its performance is verified through simulation studies. The feasibility of the proposed inverter is evaluated experimentally with a 2.4-kW prototype.

• Journal of Power Electronics
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• v.19 no.1
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• pp.168-178
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• 2019

Discrete space vector modulation (DSVM) is an effective method to improve the steady-state performance of the finite control set predictive control for permanent magnet synchronous motor drive systems. However, it requires complex computations due to the presence of numerous virtual voltage vectors. This paper proposes an improved finite control set model-free predictive control using DSVM to reduce the computational burden. First, model-free deadbeat current control is used to generate the reference voltage vector. Then, based on the principle that the voltage vector closest to the reference voltage vector minimizes the cost function, the optimal voltage vector is obtained in an effective way which avoids evaluation of the cost function. Additionally, in order to implement double-objective control, a two-level decisional cost function is designed to sequentially reduce the stator currents tracking error and the inverter switching frequency. The effectiveness of the proposed control is validated based on experimental tests.

• Journal of IKEEE
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• v.13 no.2
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• pp.208-215
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• 2009

The high efficiency power management IC(PMIC) with DT-CMOS(Dynamic Threshold voltage MOSFET) switching device for portable application is proposed in this paper. Because portable applications need high output voltages and low output voltage, Boost converter and Buck converter are embedded in One-chip. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. DTMOS with low on-resistance is designed to decrease conduction loss. Boost converter and Buck converter, are based on Voltage-mode PWM control circuits and low on-resistance switching device, achieved the high efficiency near 92.1% and 95%, respectively, at 100mA output current. And Step-down DC-DC converter in stand-by mode below 1mA is designed with LDO in order to achive high efficiency.

• Korean Journal of Optics and Photonics
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• v.35 no.5
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• pp.210-217
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• 2024

We investigate the effects of mid-spatial frequency wavefront errors on the modulation transfer function (MTF) of optical imaging systems such as airborne cameras and astronomical telescopes. To reduce the prediction error of the MTF, an improved Shannon approximation is proposed. The Shannon approximation is useful for low-order wavefront errors, but it has limitations in predicting MTF with high-order wavefront errors, especially those caused by mid-spatial frequency errors from the manufacturing process of aspheric optical components. In this study, we analyze the impacts of concentric ring-shaped mid-spatial frequency wavefront errors on the MTF using MATLAB and Code V simulations and propose a method to improve the Shannon approximation, which has a new correction factor (K-factor).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.8
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• pp.739-746
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• 2005

When we design a binary phase holographic optical low-pass filter (HOLF), the phase difference is generally set to be $\pi$ to optimize the diffraction efficiency. However, the phase difference of real HOLF mostly deviate from $\pi$ by the error in the fabrication process. The deviation causes the (0,0)-th order diffracted beam to increase, which results In raising the diffraction efficiency. To study the effects of the phase error on the performance of HOLF, we calculated the MTF of HOLF for various phase differences. The results show that the phase error of 10 $\%$ makes little change in the filtering characteristics of HOLF. Considering the filtering by lens and CCD, the effects of the phase error becomes much smaller. To confirm it experimentally, we fabricated HOLFs for various phase differences. After installing it in a digital camera, we take picture of test targets and observe the Moire fringes and the resolution. The results agree with our prediction.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.165-168
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• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.9
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• pp.847-851
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• 2011

In this paper, a novel IQ modulator that precisely controls the magnitude and phase of input signals is proposed. The proposed IQ modulator consists of low phase deviation attenuators, a splitter, and a combiner. In order to overcome the phase deviation characteristics found in conventional attenuators, a novel phase compensation technique has been adopted and mathematically analyzed. Linear vector arrays along the center point with large magnitude output signal variations in a full $360^{\circ}$ phase control are achieved on a polar plane by the proposed IQ modulator.

• Journal of Power Electronics
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• v.10 no.2
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• pp.155-164
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• 2010

This paper presents a voltage control algorithm for a hybrid multilevel inverter based on a staged-perception of the inverter voltage vector diagram. The algorithm is applied to control a three-stage eighteen-level hybrid inverter, which has been designed with a maximum number of symmetrical levels. The inverter has a two-level main stage built using a conventional six-switch inverter and medium- and low- voltage three-level stages constructed using cascaded H-bridge cells. The distinctive feature of the proposed algorithm is its ability to avoid the undesirable high switching frequency for high- and medium- voltage stages despite the fact that the inverter's dc sources voltages are selected to maximize the number of levels by state redundancy elimination. The high- and medium- voltage stages switching algorithms have been developed to assure fundamental switching frequency operation of the high voltage stage and not more than few times this frequency for the medium voltage stage. The low voltage stage is controlled using a SVPWM to achieve the reference voltage vector exactly and to set the order of the dominant harmonics. The inverter has been constructed and the control algorithm has been implemented. Test results show that the proposed algorithm achieves the desired features and all of the major hypotheses have been verified.