• The Bulletin of The Korean Astronomical Society
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• v.43 no.1
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• pp.56.3-56.3
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• 2018

The present study formulates the theory of spontaneously emitted electromagnetic fluctuations in magnetized plasmas containing particles with an anisotropic suparthermal (bi-Kappa) velocity distribution function. The formalism is general applying for an arbitrary wave vector orientation and wave polarization, and for any wave-frequency range. As specific applications, the high-frequency electromagnetic fluctuations emitted in the upper-hybrid and multiple harmonic electron cyclotron frequency range are evaluated. The fluctuations for low-frequency are also applied, which include the kinetic $Alfv\acute{e}n$, fast magnetosonic/whistler, kinetic slow mode, ion Bernstein cyclotron modes, and higher-order modes. The model predictions are confirmed by a comparison with particle-in-cell simulations. The study describes how energetic particles described by kappa velocity distribution functions influence the spectrum of high and low frequency fluctuations in magnetized plasmas. The new formalism provides quantitative analysis of naturally occurring electromagnetic fluctuations, and contribute to an understanding of the electromagnetic fluctuations observed in space plasmas, where kappa-distributed particles are ubiquitous.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.343-346
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• 2002

In recent, complex SVPWM (Space Vector PWM) algorithm can be easily implemented by high performance microprocessor and DSP. Various SVPWM techniques are widely studied due to the advantages of low harmonic distortion and high use ratio of D.C. link voltage. Most of various studies for improving of VS-PWM inverter performance are concentrated about switching pattern and zero pulse pattern split algorithms. However, dc link voltage that is determined at rated load and speed conditions is not proper in the low speed and under rated load. In this paper, analysis of current ripple with digitally implemented SVPWM inverter is introduced according to link voltage. The optimal link voltage in the designed inverter system and load condition is provided in order to suppress output voltage error and current ripple. As remaining the effective voltage vector interval per sampling period sufficiently, additional voltage error and current ripple are suppressed. The proposed algorithm is verified through digital simulation and experimental results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.5
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• pp.527-534
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• 1987

Two phase voltage controlled oscillation was realized by using the Electronic analog simulation of nonlinear simultaneous 2st order equation in terms of vibration and it's usefullness was sustined. Sinde it is complex and expensive to implement the circuits actually which composits and multiplicate the two phase signal squared respectively, this paper is obtained the simplificotion and switching circuit. The circuit introducced in this paper had propotionality of frequency to control input voltage, rapid response time, and little phase error, also this circuit operated with very low THD(Total Harmonic Distortion) and constant amplitude at higher than 10 :1 of frequency ratio.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.367-368
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• 2015

This paper introduces a shunt active power filter with a small DC bus capacitor by adding additional low-pass filter (LPF). The DC link voltage fluctuation is impressively suppressed with a small value in spite of the low value of DC-link capacitor under the steady-state condition. Consequently, the cost and volume of power converter are significantly reduced thanks to the reduced value of DC-bus capacitor. On the other hand, an indirect control strategy is used to maintain grid-side current when non-linear loads are connected to the system. By using proportional-integral (PI) and modified repetitive controller (RC) in dq0 frame, the calculation time is greatly decreased by 6 times compared with the conventional RC, and the number of measurement devices is also minimized. As a result, the acquired total harmonic distortion (THD) is lower than 2% regardless of the load conditions. Simulation results are carried out in order to verify the effectiveness of the proposed control strategy.

• Proceedings of the KIEE Conference
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• 1998.11a
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• pp.121-124
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• 1998

Front end AC to DC converters of the boost type are used in traction applications for generating the DC link for the inverters. A GTO based converter is usually switched with a switching frequency of 300 to 500Hz, resulting in low frequency harmonic problems. In order to avoid this, multiple converters with Phase shifted carrier waveforms are used to suppress the low frequency harmonics. A detailed study of an AC to DC converter, with two converters parallely operated with Phase shifted carrier wave farms is Presented in this paper.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.492-498
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• 2017

In this paper, we integrate a divide-by-3 injection-locked frequency divider (ILFD) in CMOS technology with a $0.18-{\mu}m$ BiCMOS process. We propose a self-injection technique that utilizes harmonic conversion to improve the locking range, phase-noise, and input sensitivity simultaneously. The proposed self-injection technique consists of an odd-to-even harmonic converter and a feedback amplifier. This technique offers the advantage of increasing the injection efficiency at even harmonics and thus realizes the low-power implementation of an odd-order division ILFD. The measurement results using the proposed self-injection technique show that the locking range is increased by 47.8% and the phase noise is reduced by 14.7 dBc/Hz at 1-MHz offset frequency with the injection power of -12 dBm. The designed divide-by-3 ILFD occupies $0.048mm^2$ with a power consumption of 18.2-mW from a 1.8-V power supply.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.11 no.1
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• pp.76-81
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• 2012

Ultrasonic metal welding is one of the welding methods which welds metal by applying high frequency vibrational energy into specific area at constant pressure, avaliable in room temperature and low temperature. Ultrasonic metal welder is consisted of power supply, transducer, booster, and horn. Precise designing is required since each parts' shape, length and mass can affect driving frequency and vibration mode. This paper focused to horn design, its length L was set to 62mm by calculating vibration equation. By performing modal analysis with various shape variable b times integer, when length of b is 30mm the output was 39,599Hz at 10th mode. Also by performing harmonic response analysis, the frequency response result was 39,533Hz, which was similar to modal analysis result. In order to observe the designed horn's performance, about 4,000 voltage data was obtained from a light sensor and was analyzed by FFT analysis using Origin Tool. The result RMS amplitude was approximately 8.5${\mu}m$ at 40,000Hz, and maximum amplitude was 12.3${\mu}m$. Therefore, it was verified that the ultrasonic metal welding horn was optimally designed.

• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.2
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• pp.189-197
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• 2011

As a multidisciplinary study encompassing oceanography and history, we have attempted to reanalyze the course of a historical navel battle, Myungryang Naval Battle(September 16th, 1597 according to the lunar calendar) through hindcasting the paleo-tidal currents and -tides(PTC). Firstly, we conducted harmonic analysis using 6-month current data observed at Uldolmok and 1-year elevation data provided by Korea Ocean Research and Development Institute in order to understand their characteristics and to hindcast the PTC. Observation results show that Uldolmok, ~300m wide, relatively narrow channel, is characterized by a flood-dominant mixed mainly semidiurnal tidal regime induced by relatively-strong shallow water constituents, showing closely a standing wave type of tidal current. Further, we hindcasted PTC on the day of Myungryang Naval Battle. Our results were compared and discussed with results(time and speeds of maximum(flood and ebb) currents and high and low water times) of the previous studies estimated from different methods. Lastly, we reconstruct the course of the event of Myungryang Naval Battle recorded in the Admiral Sun-Sin Yi's War Diary(Nangjung Iigi in Korean) based on our hindcasting results.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1231-1243
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• 2017

Grid-interactive power converters are normally synchronized with the grid using phase-locked loops (PLLs). The performance of the PLLs is affected by the non-ideal conditions in the sensed grid voltage such as harmonics, frequency deviations and the dc offsets in single-phase systems. In this paper, a single-phase PLL is presented to mitigate the effects of these non-idealities. This PLL is based on the popular second order generalized integrator (SOGI) structure. The SOGI structure is modified to eliminate the effects of input dc offsets. The resulting SOGI structure has a high-pass filtering property. Hence, this PLL is termed as a high-pass generalized integrator based PLL (HGI-PLL). It has fixed parameters which reduces the implementation complexity and aids in the implementation in low-end digital controllers. The HGI-PLL is shown to have the lowest resource utilization among the SOGI based PLLs with dc cancelling capability. Systematic design methods are evolved leading to a design that limits the unit vector THD to within 1% for given non-ideal input conditions in terms of frequency deviation and harmonic distortion. The proposed designs achieve the fastest transient response. The performance of this PLL has been verified experimentally. The results agree with the theoretical prediction.