• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.419-426
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• 2014

This paper proposes a high-throughput encoding process and encoder architecture for quasi-cyclic low-density parity-check codes in IEEE 802.11ac standard. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase the encoding throughput. A low complexity cyclic shifter is also proposed to minimize the hardware overhead of combinational logic in the encoder architecture. In IEEE 802.11ac systems, the proposed encoder is rate compatible to support various code rates and codeword block lengths. The proposed encoder is implemented with 130-nm CMOS technology. For (1944, 1620) irregular code, 7.7 Gbps throughput is achieved at 100 MHz clock frequency. The gate count of the proposed encoder core is about 96 K.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.4
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• pp.79-89
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• 2010

Recently, distributed video coding (DVC) has been actively studied for low complexity video encoder. The complexity of the encoder in DVC is much simpler than that of traditional video coding schemes such as H.264/AVC, but the complexity of the decoder in DVC increases. In this paper, we propose the Region-Of-Interest (ROI) based DVC with low decoding complexity. The proposed scheme uses the ROI, the region the motion of objects is quickly moving as the input of the Wyner-Ziv (WZ) encoder instead of the whole WZ frame. In this case, the complexity of encoder and decoder is reduced, and the bite rate decreases. Experimental results show that the proposed scheme obtain 0.95 dB as the maximum PSNR gain in Hall Monitor sequence and 1.87 dB in Salesman sequence. Moreover, the complexity of encoder and decoder in the proposed scheme is significantly reduced by 73.7% and 63.3% over the traditional DVC scheme, respectively. In addition, we employ the layered belief propagation (LBP) algorithm whose decoding convergence speed is 1.73 times faster than belief propagation algorithm as the Low-Density Parity-Check (LDPC) decoder for low decoding complexity.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.3
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• pp.87-95
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• 2010

Portable multi-media products which can service the highest audio-quality by using lossless audio codec has been released and the international lossless codecs, MPEG-4 audio lossless coding(ALS) and MPEG-4 scalable lossless coding(SLS), were standardized by MPEG in 2006. The simple profile of MPEG-4 ALS, it supports up to stereo, was defined by MPEG in 2009. The lossless audio codec should have low-complexity in stereo to be widely used in portable multi-media products. But the previous researches of MPEG-4 ALS have focused on an improvement of compression ratio, a complexity reduction in multi-channels coding, and a selection of linear prediction coefficients(LPCs) order. In this paper, the complexity and compression ratio of MPEG-4 ALS encoder is analyzed in simple profile of MPEG-4 ALS, the method to reduce a complexity of MPEG-4 ALS encoder is proposed. Based on an analysis of complexity of MPEG-4 ALS encoder, the complexity of short-term prediction filter of MPEG-4 ALS encoder is reduced by using the low-complexity filter that is proposed in previous research to reduce the complexity of MPEG-4 ALS decoder. Also, we propose a joint coding decision method, it reduces the complexity and keeps the compression ratio of MPEG-4 ALS encoder. In proposed method, the operation of joint coding is decided based on the relation between cross-correlation of residual and compression ratio of joint coding. The performance of MPEG-4 ALS encoder that has the method and low-complexity filter is evaluated by using the MPEG-4 ALS conformance test file and normal music files. The complexity of MPEG-4 ALS encoder is reduced by about 24% by comparing with MPEG-4 ALS reference encoder, while the compression ratio by the proposed method is comparable to MPEG-4 ALS reference encoder.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2467-2470
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• 2003

This paper presents a new structure of MPEG-4 AAC encoder. The proposed encoder directly shapes quantization noise distribution according to the energy distribution curve and thereafter performs adjustment of the offset level of the noise distribution to meet the given bit rate. The direct noise shaping and the bit rate matching scheme of the proposed encoder algorithm significantly alleviate the problem of conventional encoder's processing burden related with the employment of the precise psychoacoustic model and iteration intensive quantizer. The encoder algorithm is implemented on ARM processor with fixed-feint arithmetic operations. The audio quality of the implemented system is observed comparable to those of commercially available encoders, white the complexity of the implementation is drastically reduced in comparison to the conventional encoder systems.

• ETRI Journal
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• v.26 no.2
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• pp.122-135
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• 2004

Although frame-based MPEG-4 video services have been successfully deployed since 2000, MPEG-4 video coding is now facing great competition in becoming a dominant player in the market. Object-based coding is one of the key functionalities of MPEG-4 video coding. Real-time object-based video encoding is also important for multimedia broadcasting for the near future. Object-based video services using MPEG-4 have not yet made a successful debut due to several reasons. One of the critical problems is the coding complexity of object-based video coding over frame-based video coding. Since a video object is described with an arbitrary shape, the bitstream contains not only motion and texture data but also shape data. This has introduced additional complexity to the decoder side as well as to the encoder side. In this paper, we have analyzed the current MPEG-4 video encoding tools and proposed efficient coding technologies that reduce the complexity of the encoder. Using the proposed coding schemes, we have obtained a 56 percent reduction in shape-coding complexity over the MPEG-4 video reference software (Microsoft version, 2000 edition).

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1736-1739
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• 2002

The advanced in semiconductor, hardware, and software technologies enables the integration of more com- plex systems and the increasing design complexity. As system design complexity becomes more complicated, System-level design based on the If block and processor model is more needed in most of the RTL level or low level. In this paper, we present a novel approach fur the system-level design, which satisfies the various required constraints and an optimization method of image encoder based on codesign of function, algorithm, and architecture. In addition, we show an MPEG-4 encoder as a design case study. The best tradeoffs between algorithm and architecture are necessary to deliver the design with satisfying performance and area constraints. The evaluations provide the effective optimization of motion estimation, which is in charge of an amount of performance in the MPEG-4 encoder module.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.252-254
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• 2007

In this paper, we will introduce an encoding algorithm of LDPC Codes in Direct-Sequence UWB systems. We evaluate the performance of the coded systems in an AWGN channel. This new algorithm is based on the Jacket matrics. Mathematically let A = ($a_{kl}$) be a matnx, if $A^{-1}$ = $(a^{-1}_{kl})^r$,then the matrix A is a Jacket matrix. If the Jacket matrices if Low density, the inverse matrices is also Low density which is very important to the introduced encoding algorithm.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.244-249
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• 2010

The design of error correction code with low complexity has a good attraction for next generation multi-level cell flash memory. Sharing sub-expressions is effective method to reduce complexity and chip size. This paper proposes a new design method of m-bit parallel BCH encoder based on serial linear feedback shift register structure with low complexity using sub-expression. In addition, general algorithm for obtaining the sub-expression is introduced. The sub-expression can be expressed by matrix operation between sub-matrix of generator matrix and sum of two different variables. The number of the sub-expression is restricted by. The obtained sub-expressions can be shared for implementation of different m-parallel BCH encoder. This paper is not focused on solving a problem (delay) induced by numerous fan-out, but complexity reduction, expecially the number of gates.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.61-69
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• 2009

This paper presents the design results of a low complexity and high throughput LDPC encoder structure. In order to solve the high complexity problem of the LDPC encoder, a simplified matrix-vector multiplier is proposed instead of the conventional complex matrix-vector multiplier. The proposed encoder also adopts a partially parallel structure and performs column-wise operations in matrix-vector multiplication to achieve high throughput. Implementation results show that the proposed architecture reduces the number of logic gates and memory elements by 37.4% and 56.7%, compared with existing five-stage pipelined architecture. The proposed encoder also supports 800Mbps throughput at 40MHz clock frequency which is improved about three times more than the existing architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11C
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• pp.901-906
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• 2010

Low density parity check (LDPC) code, first introduced by Gallager and re-discovered by MacKay et al, has attracted researcher's interest mainly due to their performance and low decoding complexity. It was remarkable that the performance is very close to Shannon capacity limit under the assumption of having long codeword length and iterative decoder. However, comparing to turbo codes widely used in the current mobile communication, the encoding complexity of LDPC codes has been regarded as the drawback. This paper proposes a solution for DVB-S2 LDPC encoder to reduce the encoder latency. We use the fast IRA encoder that use the transformation of the parity check matrix into block-wise form and the partial parallel process to reduce the number of system clocks for the IRA code encoding. We compare the proposed encoder with the current DVB-S2 encoder to show that the performance of proposal is better than that of the current DVB-S2 encoder.