• Journal of Power Electronics
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• v.7 no.1
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• pp.81-88
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• 2007

This paper presents a new approach to the automatic control of the turn-off angle used to excite the Switched Reluctance Motor (SRM) employed in electric vehicles (EV). The controller selects the turn-off angle that supports and improves the performance of the motor drive system. This control scheme consisting of classical current control and speed control depends on a lookup table to take the best result of the motor. The turn-on angle of the main switches of the inverter is fixed at $0^{\circ}C$ and the turn-off angle is variable depending on the reference speed. The motor, inverter and control system are modeled in Simulink to demonstrate the operation of the system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.533-536
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• 2005

MAP algorithm is known for optimal decoding algorithm of Turbo codes, but it has very large computational complexity and delay. Generally log-MAP algorithm is used in order to overcome the defect. In this paper we propose modified scheme of the state metric calculation block which can improve the computation speed in log-MAP decoder and simple linear offset unit without using LUT. The simulation results show that the operation speed of the proposed scheme is improved as compared with that of the past scheme.

• The Journal of the Acoustical Society of Korea
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• v.23 no.8
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• pp.554-561
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• 2004

As the technologies of semiconductor and multimedia communication have been improved. the high-quality video and the multi-channel audio have been highlighted. MPEG Audio Layer 3 decoder has been implemented as a Processor using a standard. Since the synthesis filter of MPEG-1 Audio Layer 3 decoder requires the most outstanding operation in the entire decoder. the synthesis filter that can reduce the amount of operation is needed for the design of the high-speed processor. Therefore, in this paper, the synthesis filter. the most important part of MPEG Audio, is materialized in FPGA using the method of DAULT (distributed arithemetic look-up table). For the design of high-speed synthesis filter, the DAULT method is used instead of a multiplier and a Pipeline structure is used. The Performance improvement by 30% is obtained by additionally making the result of multiplication of data with cosine function into the table. All hardware design of this Paper are described using VHDL (VHIC Hardware Description Language) Active-HDL 6.1 of ALDEC is used for VHDL simulation and Synplify Pro 7.2V is used for Model-sim and synthesis. The corresponding library is materialized by XC4013E and XC4020EX. XC4052XL of XILINX and XACT M1.4 is used for P&R tool. The materialized processor operates from 20MHz to 70MHz.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.5
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• pp.1198-1212
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• 2013

Network virtualization enables autonomous and heterogeneous Virtual Networks (VNs) to co-exist on a shared physical substrate. In a Network Virtualization Environment (NVE), the fact that individual VNs are underpinned by diverse naming mechanisms brings about an obvious challenge for transparent communication across multiple VN domains due to the complexity of uniquely identifying users. Existing solutions were mainly proposed compatible to Internet paradigm with little consideration of their applications in a virtualized environment. This calls for a scalable and efficient naming framework to enable consistent communication across a large user population (fixed or mobile) hosted by multiple VNs. This paper highlights the underlying technical requirements and presents a scalable Global Naming Framework (GNF), which (1) enables transparent communication across multiple VNs owned by the same or different SPs; (2) supports communication in the presence of dynamics induced from both VN and end users; and (3) greatly reduces the network operational complexity (space and time). The suggested approach is assessed through extensive simulation experiments for a range of network scenarios. The numerical result clearly verifies its effectiveness and scalability which enables its application in a large-scale NVE without significant deployment and management hurdles.

• The KIPS Transactions:PartD
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• v.10D no.6
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• pp.1017-1024
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• 2003

Jini is a promising HomeNetworking middleware of computing environment based on Java Technology. To support Homenetwork service based on Jini, Jini device requires a successive operation and complicated management. In this paper, our service management system is a service provider component and lookup service component including automation module. Our automatin module privide searching and setting function of a library, runtime environment and class file system cinfiguration information for Jini service. Our system can be accomplished by automation of runtime environment, simplification of service management structure, visualization of service execution.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.5
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• pp.297-305
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• 2015

AFLS (Adaptive front lighting System) is being applied to improve safety in driving automotive at night. Safe embedded system for controlling head-lamp has to be tightly designed by considering safety requirement of hardware-dependent software, which is embedded in automotive ECU(Electronic Control Unit) hardware under severe environmental noise. In this paper, we propose an adaptive headlight controller with newly-designed symmetric angle sensor compensator, which is integrated with ECU-based adaptive front light system. The proposed system, on which additional backup hardware and emergency control algorithm are integrated, effectively detects abnormal situation and restore safe status of controlling the light-angle in AFLS operations by comparing result in symmetric angle sensor. The controlled angle value is traced into internal memory in runtime and will be continuously compared with the pre-defined lookup table (LUT) with symmetric angle value, which is used in normal operation. The watch-dog concept, which is based on using angle sensor and control-value tracer, enables quick response to restore safe light-controlling state by performing the backup sequence in emergency situation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1891-1898
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• 2013

To efficiently execute 3D graphic APIs, such as OpenGL and Direct3D, special purpose arithmetic unit(SFU) which supports floating-point sine, cosine, reciprocal, inverse square root, base-two exponential, and logarithmic operations is designed. The SFU uses second order minimax approximation method and lookup table method to satisfy both error less than 2 ulp(unit in the last place) and high speed operation. The designed circuit has about 2.3-ns delay time under 65nm CMOS standard cell library and consists of about 23,300 gates. Due to its maximum performance of 400 MFLOPS and high accuracy, it can be efficiently applicable to mobile 3D graphics application.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.5
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• pp.127-135
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• 2010

In motion adaptive temporal noise reduction filtering used for reducing video noises, the strength of motion adaptive temporal filtering should be carefully controlled according to temporal movement. This paper presents a motion adaptive temporal filtering scheme based on least-square training. Each pixel is classified to a specific class code according to temporal movement, and then, an iterative least-square training method is applied for each class code to find optimal filtering coefficients. The iterative least-square training is an off-line procedure, and the trained filter coefficients are stored in a lookup table (LUT). In actual noise reduction filtering operation, after each pixel is classified by temporal movement, simple filtering operation is applied with the filter coefficients stored in the LUT according to the class code. Experiment results show that the proposed method efficiently reduces video noises without introducing blurring.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.51-57
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• 2003

The development of the communication network and the other network method can generate serious social problems. So, it is highly required to control security of network. These problems related security will be developed and keep up to confront with anti-security field such as hacking, cracking. The way to preserve security from hacker or cracker without developing new cryptographic algorithm is keeping the state of anti-cryptanalysis in a prescribed time by means of extending key-length. In this paper, we proposed M3 algorithm for the reduced processing time in the montgomery multiplication part. Proposed M3 algorithm using the matrix function M(.) and lookup table perform optionally montgomery multiplication with repeated operation. In this result, modified repeated operation part produce 30% processing rate than existed montgomery multiplicator. The proposed montgomery multiplication structured unit array method in carry generated part and variable length multiplication for eliminating bottle neck effect with the RSA cryptosystem. Therefore, this proposed montgomery multiplier enforce the real time processing and prevent outer cracking.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.102-107
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• 2007

This paper proposes a H.264/AVC entropy decoder without embedded processor nor memory fabrication process. Many researches on H.264/AVC entropy decoders require ROM or RAM fabrication process, which is difficult to be implemented in general digital logic fabrication process. Furthermore, many researches require embedded processors for bitstream manipulation, which increases area and power consumption. This papers proposes hardwired H.264/AVC entropy decoder without embedded processor, which improves data processing speed and reduces power consumption. Furthermore, its CAVLC decoder optimizes lookup table and internal buffer without embedded memory, which reduces hardware size and can be implemented in general digital logic fabrication process without ROM or RAM fabrication process. Designed entropy decoder was embedded in H.264/AVC video decoder, and it was verified to operate correctly in the system. Synthesized in TSMC 90nm fabrication process, its maximum operation frequency is 125MHz. It supports QCIF, CIF, and QVGA image format. Under slight modification of nC register and other blocks, it also support VGA image format.