• Title/Summary/Keyword: look up table

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A Study on Drawing Direction-related characteristics of Ridge by the Scanner Input Method (스캐너 입력방식에 의한 융선의 방향성 특징추출에 관한 연구)

  • 김은영;양영수;강진석;최연성;김장형
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.6 no.7
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    • pp.1113-1119
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    • 2002
  • In this paper, it was presented that broadly delivered scanner devices can also used in finger print recognition process and then modified existing steps of fingerprint image Processing. First, using the adaptive binary method, that effect was certified already, increased the effect of the results. And then, applying table mapping methods that looks for elements from look-up table, decreased the processing time, too. Finally, it was presented that ridge-direction characteristics extracted from these processes can used effectively In the area of fingerprint recognition system.

A Study on Drawing Direction-related characteristics of Ridge by the Scanner Input Method (스캐너 입력방식에 의한 융선의 방향성 특징추출에 관한 연구)

  • 김은영;양영수;강진석;김장형;최연성
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.11a
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    • pp.386-390
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    • 2002
  • In this paper, it was presented that broadly delivered scanner devices can also used in finger print recognition process and then modified existing steps of fingerprint image processing. First, using the adaptive binary method, that effect was certified already, increased the effect of the results. And then, applying table mapping methods that looks for elements from look-up table, decreased the processing time, too. Finally, it was presented that ridge-direction characteristics extracted from these processes can used effectively in the area of fingerprint recognition system.

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Failure Prediction of Metal Oxide Varistor Using Nonlinear Surge Look-up Table Based on Experimental Data

  • Kim, Young Sun
    • Transactions on Electrical and Electronic Materials
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    • v.16 no.6
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    • pp.317-322
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    • 2015
  • The metal oxide varistor (MOV) is a major component of the surge protection devices (SPDs) currently in use. The device is judged to be faulty when fatigue caused by the continuous inflow of lightning accumulates and reaches the damage limit. In many cases, induced lightning resulting from lightning strikes flows in to the device several times per second in succession. Therefore, the frequency or the rate at which the SPD is actually exposed to stress, called a surge, is outside the range of human perception. For this reason, the protective device should be replaced if it actually approaches the end of its life even though it is not faulty at present, currently no basis exists for making the judgment of remaining lifetime. Up to now, the life of an MOV has been predicted solely based on the number of inflow surges, irrespective of the magnitude of the surge current or the amount of energy that has flowed through the device. In this study, nonlinear data that shows the damage to an MOV depending on the count of surge and the amount of input current were collected through a high-voltage test. Then, a failure prediction algorithm was proposed by preparing a look-up table using the results of the test. The proposed method was experimentally verified using an impulse surge generator

Look-Up Table Based Implementations of SHA-3 Finalists: JH, Keccak and Skein

  • Latif, Kashif;Aziz, Arshad;Mahboob, Athar
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.6 no.9
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    • pp.2388-2404
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    • 2012
  • Cryptographic hash functions are widely used in many information security applications like digital signatures, message authentication codes (MACs), and other forms of authentication. In response to recent advances in cryptanalysis of commonly used hash algorithms, National Institute of Standards and Technology (NIST) announced a publicly open competition for selection of new standard Secure Hash Algorithm called SHA-3. One important aspect of this competition is evaluation of hardware performances of the candidates. In this work we present efficient hardware implementations of SHA-3 finalists: JH, Keccak and Skein. We propose high speed architectures using Look-Up Table (LUT) resources on FPGAs, to minimize chip area and to reduce critical path lengths. This approach allows us to design data paths of SHA-3 finalists with minimum resources and higher clock frequencies. We implemented and investigated the performance of these candidates on modern and latest FPGA devices from Xilinx. This work serves as performance investigation of leading SHA-3 finalists on most up-to-date FPGAs.

Set-Up model for the silicon steel cold rolling mill

  • Kim, Sang-Kyun;Won, Sang-Chul
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.1323-1326
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    • 2003
  • In this paper, we propose set-up model of silicon steel cold rolling mill. Until now, the working of Silicon Steel is operated using the look-up table value of roll force which a field operator finds by making good use of his experience. Therefore, the standardization of data and an improvement of the quality on product are very difficult. So we establish neural model using field data of various kinds of coil at each pass.

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Deriving the Fourier Transforms of Pulse Signals Through the Look-up Tables (찾아보기 목록에 의한 고차 펄스의 푸리에 변환법)

  • 오용선
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.18 no.3
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    • pp.327-338
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    • 1993
  • This paper proposes a novel method for deriving the Fourier transform pairs of high order pulses given in a generalized form. Primarily, modifying the PRS system model, we establish a new model which simplifies the process of Fourier analysis of the n-th order pulse signal, resulting in a representative relationship. In succession, we present the Frame Formula which plays a role of substituent for the parameters in table look-up procedures. Each look-up table contains all the parameters needed to obtain the Fourier transform of the corresponding pulse of any order. Regarding the amount of calculations and the complexity of procedures required to derive the transforms of pulse signals, analytically or numerically, this method is more compact and timesaving than conventional methods. When pulse has a much narrow width of equivalently higher the order of several pulses, the method presented here acts to the best of its true merit.

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Implementation of a Logic Extraction Algorithm from a Bitstream Data for a Programmed FPGA (프로그램된 FPGA의 비트스트림 데이터로부터 로직추출 알고리즘 구현)

  • Jeong, Min-Young;Lee, Jae-Heum;Jang, Young-Jo;Jung, Eun-Gu;Cho, Kyoung-Rok
    • The Journal of the Korea Contents Association
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    • v.18 no.1
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    • pp.10-18
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    • 2018
  • This paper presents a method to resynthesize logic of a programmed FPGA from a bitstream file that is a downloaded file for Xilinx FPGA (Field Programmable Gate Array). It focuses on reconfiguring the LUT (Look Up Table) logic. The bitstream data is compared and analyzed considering various situations and various input variables such as composing other logics using the same netlist or synthesizing the same logic at various positions to find a structure of the bitstream. Based on the analyzed bitstream, we construct a truth table of the LUT by implementing various logic for one LUT. The proposed algorithm extracts the logic of the LUT based on the truth table of the generated LUT and the bitstream. The algorithm determines the input and output pins used to implement the logic in the LUT. As a result, we extract a gate level logic from a bitstream file for the targeted Xillinx FPGA.

An Implementation of Real-time Image Warping Using FPGA (FPGA를 이용한 실시간 영상 워핑 구현)

  • Ryoo, Jung Rae;Lee, Eun Sang;Doh, Tae-Yong
    • IEMEK Journal of Embedded Systems and Applications
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    • v.9 no.6
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    • pp.335-344
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    • 2014
  • As a kind of 2D spatial coordinate transform, image warping is a basic image processing technique utilized in various applications. Though image warping algorithm is composed of relatively simple operations such as memory accesses and computations of weighted average, real-time implementations on embedded vision systems suffer from limited computational power because the simple operations are iterated as many times as the number of pixels. This paper presents a real-time implementation of a look-up table(LUT)-based image warping using an FPGA. In order to ensure sufficient data transfer rate from memories storing mapping LUT and image data, appropriate memory devices are selected by analyzing memory access patterns in an LUT-based image warping using backward mapping. In addition, hardware structure of a parallel and pipelined architecture is proposed for fast computation of bilinear interpolation using fixed-point operations. Accuracy of the implemented hardware is verified using a synthesized test image, and an application to real-time lens distortion correction is exemplified.

Ternary Bose - Chaudhuri - Hocquenghem (BCH) with t = 2 code for steganography (3진 BCH (Bose - Chaudhuri - Hocquenghem) 코드를 이용하는 스테가노그라피 기법)

  • Sachnev, Vasily;Choi, Yong Soo
    • Journal of Digital Contents Society
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    • v.17 no.6
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    • pp.461-469
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    • 2016
  • A novel steganography based on ternary BCH code with t = 2 is presented in this paper. Proposed method utilizes powerful BCH code with t = 2 for data hiding to the DCT coefficients from JPEG images. The presented data hiding technique uses a proposed look up table approach for searching multiple solutions for ternary BCH code with t = 2. The proposed look up table approach enables fast and efficient search for locations of DCT coefficients, which are necessary to modify for hiding data. Presented data hiding technique is the first steganography technique based on ternary BCH code. Experimental results clearly indicate advantages of using ternary BCH compared to binary BCH.