• 전자공학회논문지C
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• 제35C권1호
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• pp.1-9
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• 1998

In the circuit model that outputs are latched and input vectors are successively applied at inputs, the gate resizing approach to reduce the delay of the critical pathe may not improve the performance. Since the clock period is etermined by delays of both long and short paths in combinational circuits, the performance (clock period) can be optimized by decreasing the delay of the longest path, or increasing the delay of the shortest path. In order to achieve the desired clock period of a circuit, gates lying in sensitizable long and short paths can be selected for resizing. However, the gate selection in path sensitization approach is a difficult problem due to the fact that resizing a gate in shortest path may change the longest sensitizable path and viceversa. For feasible settings of the clock period, new algorithms and corresponding gate selection methods for resizing are proposed in this paper. Our new gate selection methods prevent the delay of the longest path from increasing while resizing a gate in the shortest path and prevent the delay of the shortest path from decreasing while resizing a gate in the longest sensitizable path. As a result, each resizing step is guaranteed not to increase the clock period. Our algorithmsare teted on ISCAS85 benchmark circuits and experimental results show that the clock period can beoptimized efficiently with out gate selection methods.

• 한국경영과학회지
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• 제18권2호
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• pp.23-43
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• 1993

This paper employs fuzzy variables instead of deterministic variables for job times in a project network. A fuzzy variable has its value restricted by a possibility distribution. This paper utilizes the triangular possibility distribution which has three estimated times. That is normal, resonable, and crash job times. This paper develops a fuzzy k-longest path algorithm, by utilizing the k-longest path algorithm. This algorithm will be useful to control the project the project network by considering the project completion possibility.

• 한국정보과학회논문지:시스템및이론
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• 제31권7호
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• pp.397-401
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• 2004

각 에지에 무게(양수, 음수, 0 가능)가 주어진 트리에서, 경로의 에지들의 무게의 합이 비음수이면서 길이가 가장 긴 경로를 구하는 문제를 해결하고자 한다. 차수가 3인 트리에서 가장 긴 비음수 경로를 찾는 Ο(n log n) 시간 알고리즘을 제시한다. n은 트리가 가지는 노드의 수이다.

• 한국정보과학회논문지:시스템및이론
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• 제33권12호
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• pp.880-884
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• 2006

각 에지에 무게(양수, 음수, 0 가능)가 주어진 트리에서, 경로의 에지들의 무게의 합이 비음수이면서 길이가 가장 긴 경로를 구하는 문제를 해결하고자 한다. 트리에서 가장 긴 비음수 경로를 찾는 O(n logn) 시간 직렬 알고리즘과 $O(log^2n)$ 시간과 O(n)개의 프로세서를 사용하는 CREW PRAM 병렬 알고리즘을 제시한다. 여기서, n은 트리가 가지는 노드의 수이다.

• 대한전기학회논문지:전력기술부문A
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• 제48권10호
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• pp.1344-1348
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• 1999

This paper proposes concurrent event propagation technique for timing analysis. The technique makes it possible to find several input vectors and sensitizable paths at the same time. The concurrent event propagation technique is based on the event driven simulation and the timing analysis technique with boolean equations. The technique propagates as many events as possible at the same time while preventing propagation of boolean terms which do not sensitize paths. Since events do not propagate through false paths, the longest path which successfully propagates events to one of the primary outputs is one of the longest sensitizable paths. The technique can speed up timing analysis by unifying path sensitization and maximum delay calculation.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제11권4호
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• pp.2149-2170
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• 2017

Application-layer Distributed Denial-of-Service (DDoS) attack is one of the leading security problems in the Internet. In recent years, the attack strategies of application-layer DDoS have rapidly developed. This paper introduces a new attack strategy named Path Vulnerabilities-Based (PVB) attack. In this attack strategy, an attacker first analyzes the contents of web pages and subsequently measures the actual response time of each webpage to build a web-resource-weighted-directed graph. The attacker uses a Top M Longest Path algorithm to find M DDoS vulnerable paths that consume considerable resources when sequentially accessing the pages following any of those paths. A detection mechanism for such attack is also proposed and discussed. A finite-state machine is used to model the dynamical processes for the state of the user's session and monitor the PVB attacks. Numerical results based on real-traffic simulations reveal the efficiency of the attack strategy and the detection mechanism.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.723-728
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• 1999

In this paper, we designed a Circular Path Built-In Self Test circuit and embedded it into a simple 8-bit microprocessor. Register cells of the microprocessor have been modified into Circular Path register cells and each register cells have been connected to form a scan chain. A BIST controller has been designed for controlling BIST operations and its operation has been verified through simulation. The BIST circuit described in this paper has increased size overhead of the microprocessor by 29.8% and delay time in the longest delay path from clock input to output by 2.9㎱.

• 전자공학회논문지A
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• 제32A권12호
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• pp.229-240
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• 1995

This paper proposes a new weighted random pattern testing technique to detect path delay faults in combinational logic circuits. When computing the probability of signal transition at primitive logic elements of CUT(Circuit Under Test) by the primary input, the proposed technique uses the information on the structure of CUT for initialization vectors and vectors generated by pseudo random pattern generator for test vectors. We can sensitize many paths by allocating a weight value on signal lines considering the difference of the levels of logic elements. We show that the proposed technique outperforms existing testing method in terms of test length and fault coverage using ISCAS '85 benchmark circuits. We also show that the proposed testing technique generates more robust test vectors for the longest and near-longest paths.

• 반도체디스플레이기술학회지
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• 제9권2호
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• pp.15-20
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• 2010

This paper deals with minimizing layout area of FPGA design. FPGAs are becoming increasingly important in the design of ASICs since they provide both large scale integration and user-programmability. This paper describes a method to obtain tight bound on the worst-case increase in area when drivers are introduced along many long wires in a layout. The area occupied by minimum-area embedding for a circuit can depend on the aspect ratio of the bounding rectangle of the layout. This paper presents a separator-based area-optimal embeddings for FPGA graphs in rectangles of several aspect ratios which solves the longest path problem in the constraint graph.

• 대한전자공학회논문지SD
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• 제46권9호
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• pp.49-57
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• 2009

본 연구에서는 상위 수준 합성에서 시간 제약과 하드웨어 제약을 동시에 고려하여 에너지 소모를 최소로 줄이는 다중 전압스케줄링 방법을 개발하였다. 기존의 다중 전압 스케줄링에서는 임계 경로에 있는 연산에 대해 높은 전압을 할당하고, 임계 경로에 있지 않은 연산에 대해서는 낮은 전압을 할당하는 방법을 주로 사용하였다. 우리는 다중 전압 리스트 스케줄링을 기반으로 simulated annealing기법을 적용하여 임계 경로상의 연산인지와 관계없이 자유롭게 여러 전압을 할당하여 최적화함으로서 저전력 스케줄링 결과를 얻을 수 있었다. 계산 시간 제한에 여유가 있을 때에는 전반적으로 낮은 전압을 사용하여 에너지 소모를 더욱 낮출 수 있다. 그리고 후처리 과정을 통해 추가의 에너지 감소를 얻을 수 있었다. 경우에 따라, 전압 level shifter 수를 줄일 필요가 있으므로 비용 함수에 가중치를 줄 수 있도록 하였다. 예를 들어, level shifter 에너지 소모에 6배의 가중치를 주면, 전압 level shifter 수는 약 24%, shifter 에너지 소모는 약 20% 정도 감소한다. 이를 이용하여 전체 에너지 소모와 level shifter 사용횟수의 tradeoff가 가능하다.