• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.1
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• pp.1-9
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• 1998

In the circuit model that outputs are latched and input vectors are successively applied at inputs, the gate resizing approach to reduce the delay of the critical pathe may not improve the performance. Since the clock period is etermined by delays of both long and short paths in combinational circuits, the performance (clock period) can be optimized by decreasing the delay of the longest path, or increasing the delay of the shortest path. In order to achieve the desired clock period of a circuit, gates lying in sensitizable long and short paths can be selected for resizing. However, the gate selection in path sensitization approach is a difficult problem due to the fact that resizing a gate in shortest path may change the longest sensitizable path and viceversa. For feasible settings of the clock period, new algorithms and corresponding gate selection methods for resizing are proposed in this paper. Our new gate selection methods prevent the delay of the longest path from increasing while resizing a gate in the shortest path and prevent the delay of the shortest path from decreasing while resizing a gate in the longest sensitizable path. As a result, each resizing step is guaranteed not to increase the clock period. Our algorithmsare teted on ISCAS85 benchmark circuits and experimental results show that the clock period can beoptimized efficiently with out gate selection methods.

• Journal of the Korean Operations Research and Management Science Society
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• v.18 no.2
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• pp.23-43
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• 1993

This paper employs fuzzy variables instead of deterministic variables for job times in a project network. A fuzzy variable has its value restricted by a possibility distribution. This paper utilizes the triangular possibility distribution which has three estimated times. That is normal, resonable, and crash job times. This paper develops a fuzzy k-longest path algorithm, by utilizing the k-longest path algorithm. This algorithm will be useful to control the project the project network by considering the project completion possibility.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.7
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• pp.397-401
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• 2004

In an edge-weighted(positive, negative, or zero weights are possible) tree, we want to solve the problem of finding a longest path such that the sum of the weights of the edges in the path is non-negative. We present an algorithm to find a longest non-negative path of a degree 3 tree in Ο(n log n) time, where n is the number of nodes in the tree.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.12
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• pp.880-884
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• 2006

In an edge-weighted(positive, negative, or zero weights are possible) tree, we want to solve the problem of finding a longest path such that the sum of the weights of the edges in tile path is non-negative. To find a longest non-negative path of a tree we present a sequential algorithm with O(n logn) time and a CREW PRAM parallel algorithm with $O(log^2n)$ time and O(n) processors. where n is the number of nodes in the tree.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.10
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• pp.1344-1348
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• 1999

This paper proposes concurrent event propagation technique for timing analysis. The technique makes it possible to find several input vectors and sensitizable paths at the same time. The concurrent event propagation technique is based on the event driven simulation and the timing analysis technique with boolean equations. The technique propagates as many events as possible at the same time while preventing propagation of boolean terms which do not sensitize paths. Since events do not propagate through false paths, the longest path which successfully propagates events to one of the primary outputs is one of the longest sensitizable paths. The technique can speed up timing analysis by unifying path sensitization and maximum delay calculation.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.4
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• pp.2149-2170
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• 2017

Application-layer Distributed Denial-of-Service (DDoS) attack is one of the leading security problems in the Internet. In recent years, the attack strategies of application-layer DDoS have rapidly developed. This paper introduces a new attack strategy named Path Vulnerabilities-Based (PVB) attack. In this attack strategy, an attacker first analyzes the contents of web pages and subsequently measures the actual response time of each webpage to build a web-resource-weighted-directed graph. The attacker uses a Top M Longest Path algorithm to find M DDoS vulnerable paths that consume considerable resources when sequentially accessing the pages following any of those paths. A detection mechanism for such attack is also proposed and discussed. A finite-state machine is used to model the dynamical processes for the state of the user's session and monitor the PVB attacks. Numerical results based on real-traffic simulations reveal the efficiency of the attack strategy and the detection mechanism.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.723-728
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• 1999

In this paper, we designed a Circular Path Built-In Self Test circuit and embedded it into a simple 8-bit microprocessor. Register cells of the microprocessor have been modified into Circular Path register cells and each register cells have been connected to form a scan chain. A BIST controller has been designed for controlling BIST operations and its operation has been verified through simulation. The BIST circuit described in this paper has increased size overhead of the microprocessor by 29.8% and delay time in the longest delay path from clock input to output by 2.9㎱.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.229-240
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• 1995

This paper proposes a new weighted random pattern testing technique to detect path delay faults in combinational logic circuits. When computing the probability of signal transition at primitive logic elements of CUT(Circuit Under Test) by the primary input, the proposed technique uses the information on the structure of CUT for initialization vectors and vectors generated by pseudo random pattern generator for test vectors. We can sensitize many paths by allocating a weight value on signal lines considering the difference of the levels of logic elements. We show that the proposed technique outperforms existing testing method in terms of test length and fault coverage using ISCAS '85 benchmark circuits. We also show that the proposed testing technique generates more robust test vectors for the longest and near-longest paths.

• Journal of the Semiconductor & Display Technology
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• v.9 no.2
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• pp.15-20
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• 2010

This paper deals with minimizing layout area of FPGA design. FPGAs are becoming increasingly important in the design of ASICs since they provide both large scale integration and user-programmability. This paper describes a method to obtain tight bound on the worst-case increase in area when drivers are introduced along many long wires in a layout. The area occupied by minimum-area embedding for a circuit can depend on the aspect ratio of the bounding rectangle of the layout. This paper presents a separator-based area-optimal embeddings for FPGA graphs in rectangles of several aspect ratios which solves the longest path problem in the constraint graph.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.49-57
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• 2009

In this paper, we propose a multiple voltage scheduling method which reduces energy consumption considering both timing constraints and resource constraints. In the other multiple voltage scheduling techniques, high voltage is assigned to operations in the longest path and low voltage is assigned to operations that are not on the longest path. However, in those methods, voltages are assigned to specific operations restrictively. We use a simulated annealing technique, in which several voltages are assigned to specific operations flexibly regardless of whether they are on the longest path. In this paper, a post processing algorithm is proposed to further reduce the energy consumption. In some cases, designers may want to reduce the level shifters. To make tradeoff between the total energy and the number (or energy) of level shifters weighted term can be added to the cost function. When the level shifter energy is weighted six times, for example, the number of level shifters is reduced by about 24% and their energy consumption is reduced by about 20%.