• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1964-1967
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• 2002

Recently design verification have been played an important role in the design of large scale and complex systems. In this article, we especially focus on model checking methods. Behaviors of modeled systems are generally specified by temporal formulas of computation tree logic. However. Users must know well temporal specification because the specification might be complex. We proposed method that temporal formulas are gained inductively and amounts of memory and time are reduced. Finally, we will show verification results using our proposed method.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.38-49
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• 1997

In this paper, w describe partitioning large circuits into multiple chips on the programmable FPCB for rapid prototyping. FPCBs consists of areas for FPGAs for logic and interconnect components, and the routing topology among them are predetermined. In the partition problem for FPCBs, the number of wires ofr routing among chips is fixed, which is an additonal constraints to the conventional partition problem. In order to deal with such aconstraint properly we first define a new partition problem, so called the topologybased partition problem, and then propose a heuristic method. The heuristic method is based on the simulated annealing and clustering technique. The multi-level tree clustering technique is used to obtain faster and better prtition results. In the experimental results for several test circuits, the restrictions for FPCB were all satisfied and the needed execution time was about twice the modified K-way partition method for large circuits.

• Journal of the Korean Society of Safety
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• v.18 no.4
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• pp.155-163
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• 2003

The intensity of industrial accidents has been increased while the number of industrial accidents has been decreased in theses days. It represents that we need safety guidelines based on personal attributes as well as physical attributes. This study tries to identify major causative factors for industrial accidents and to suggest an evaluation model based on personal attributes. Specifically, relationship between self-efficacy belief associated with industrial safety and other relative personal attributes has been analyzed. First, FGI(Focus Group Interview) was conducted to identify important personal attributes of industrial accidents. The questionnaire was prepared based on the results of FGI and was applied to identifying personal attributes. The relationship between personal attributes identified in this study and self-efficacy belief was assessed using fuzzy logic and fault tree analysis. The results of the assessment showed that self-efficacy belief was closely associated with industrial accidents. Specifically, workers with accident experience had higher level of self-efficacy beliefs than workers without accident experience.

• Korean System Dynamics Review
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• v.12 no.4
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• pp.63-92
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• 2011

The purpose of this paper is to investigate a possibility of applying multimethodological approach for solving a dilemma. The motivation of this attempt is that the two different approaches, the system dynamics and the theory of constraints, resemble each other in having mental models for describing the target system and using graphic tools for representing those mental models. After a brief discussion on the comparison of the two approaches, a combined method applying to the problem of dilemma is suggested. For an experimental example, the proposed approach is applied to the sales and finance conflict on an inventory issue. The study shows that the suggested approach is able to complement each other's drawbacks. Especially constructing a stock-and-flow model and implementing a computer simulation would be very useful for quantifying the system's behavior which is hardly tracked down when applying the theory of constraints alone.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.8
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• pp.1457-1465
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• 2016

A RCM approach to maintenance of the catenary system of electric railway is proposed. The proposed RCM approach provides a maintenance-oriented FMECA procedure to derive critical failure modes by analyzing failure effects and a RCM decision logic tree to suggest optimal maintenance works for the derived failure modes. By applying the proposed RCM procedures to the catenary system of high speed railway, it is suggested that strand breaks of dropper and voltage equalizing wire, and trolly wire wear-out are the critical failure modes for whom maintenance works based on condition monitoring should be applied instead of conventional time-based preventive maintenance. It is also proposed by reliability analysis that replacement time of dropper can be reduced from 18 years to 10 years. These results show that the proposed RCM approach can optimize the maintenance procedures of catenary system.

• The Transactions of the Korea Information Processing Society
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• v.5 no.7
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• pp.1908-1922
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• 1998

본 논문은 논리언어 프로그램의 효율적인 클로즈(Clause) 인덱싱을 위한 컴파일 기법에 대한 체계적인 접근방법을 제시한다. 본 접근방법의 핵심으로서 노드당 평균 병렬도와 클로즈 수행시도(clause trial) 횟수를 정확하게 나타낼 수 있는 기법으로서 인덱싱트리(Indexign Tree)를 제안한다. 인덱싱트리는 인덱싱 수행 시에 인덱싱을 위한 지시어(Instruction)의 수행 결과로 프로그램으 컨트롤이 실패처리코드로 이동하는 경우도 정량적으로 나타내 준다. 인덱싱트리를 사용하여 논리 프로그램을 위한 대표적인 가상머신인 WAM(Warren Abstract Machine)을 분석한 결과, WAM에서 사용하는 인덱싱 기법이 논리 프로그램의 병렬 처리에 있어 탐색트리의 병렬도를 감소시키며, 또한 스케쥴링의 효율성을 저하시키는 결점을 내포하고 있음을 발견할 수 있었다. 이러한 결점을 해결하기 위하여 본 논문은 플랫 인덱싱이라는 새로운 인덱싱 기법을 제안하고 이것을 실제 논리언어 컴파일러에 구현하여 측정한 향상 및 분석 결과를 보여준다.

• Applied Biological Chemistry
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• v.50 no.4
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• pp.245-252
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• 2007

FTA (fault tree analysis), an analytical method for system failure management, was employed in the management of faults in running PCR analysis. PCR is executed through several processes, in which the process of PCR machine operation was selected for the analysis by FTA. The reason for choosing the simplest process in the PCR analysis was to adopt it as a first trial to test a feasibility of the FTA approach. First, fault events-top event, intermediate event, basic events-were identified by survey on expert knowledge of PCR. Then those events were correlated deductively to build a fault tree in hierarchical structure. The fault tree was evaluated qualitatively and quantitatively, yielding minimal cut sets, structural importance, common cause vulnerability, simulation of probability of occurrence of top event, cut set importance, item importance and sensitivity. The top event was 'errors in the step of PCR machine operation in running PCR analysis'. The major intermediate events were 'failures in instrument' and 'errors in actions in experiment'. The basic events were four events, one event and one event based on human errors, instrument failure and energy source failure, respectively. Those events were combined with Boolean logic gates-AND or OR, constructing a fault tree. In the qualitative evaluation of the tree, the basic events-'errors in preparing the reaction mixture', 'errors in setting temperature and time of PCR machine', 'failure of electrical power during running PCR machine', 'errors in selecting adequate PCR machine'-proved the most critical in the occurrence of the fault of the top event. In the quantitative evaluation, the list of the critical events were not the same as that from the qualitative evaluation. It was because the probability value of PCR machine failure, not on the list above though, increased with used time, and the probability of the events of electricity failure and defective of PCR machine were given zero due to rare likelihood of the events in general. It was concluded that this feasibility study is worth being a means to introduce the novel technique, FTA, to the management of faults in running PCR analysis.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.56-65
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• 2016

In this paper, in order to reduce the delay and area of the partial product accumulation (PPA) of the parallel decimal multiplier, a tree architecture that composed by multi-operand decimal CSAs and improved CLA is proposed. The proposed tree using multi-operand CSAs reduces the partial product quickly. Since the input range of the recoder of CSA is limited, CSA can get the simplest logic. In addition, using the multi-operand decimal CSAs to add decimal numbers that have limited range in specific locations of the specific architecture can reduce the partial products efficiently. Also, final BCD result can be received faster by improving the logic of the decimal CLA. In order to evaluate the performance of the proposed partial product accumulation, synthesis is implemented by using Design Complier with 180 nm COMS technology library. Synthesis results show the delay of the proposed partial product accumulation is reduced by 15.6% and area is reduced by 16.2% comparing with which uses general method. Also, the total delay and area are still reduced despite the delay and area of the CLA are increased.

• Journal of the Korean earth science society
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• v.37 no.1
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• pp.52-61
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• 2016

The purpose of the study was to create a probabilistic seismic hazard map using the input data that reflected the seismo-tectonic characteristics of the Korean Peninsula by applying USGS program (Harmsen (2008). The program was partly modified for the purpose of this study. The uncertainty of input parameters given by specialists was reflected in calculating the seismic hazard values by logic tree method. The general pattern of PGA was quite sensitive and similar to the shape of areal source. The probabilistic seismic hazard map showed the contour distribution of peak acceleration (%g) with 10% probability of exceedance in 5, 10, 20, 50, 100, 250, and 500 years. The result showed that the peak ground acceleration (PGA) values of the northern peninsula were almost half values of the southern peninsula except Hwanghae province. The general trend of the hazard map extended in the direction of NW-SE from Whanghae province to south-eastern regions of the peninsula. The values in northern part of Kangwon province were relatively lower than other areas in the southern peninsula. The maps produced through this study are considered valuable in regulating the seismic safety of the major facilities in the Korean Peninsula.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.20-35
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• 2016

In this paper, in order to reduce the delay and area of the partial product accumulation (PPA) of the parallel decimal multiplier, a tree architecture that composed by multi-operand decimal CSAs and improved CLA is proposed. The proposed tree using multi-operand CSAs reduces the partial product quickly. Since the input range of the recoder of CSA is limited, CSA can get the simplest logic. In addition, using the multi-operand decimal CSAs to add decimal numbers that have limited range in specific locations of the specific architecture can reduce the partial products efficiently. Also, final BCD result can be received faster by improving the logic of the decimal CLA. In order to evaluate the performance of the proposed partial product accumulation, synthesis is implemented by using Design Complier with 180 nm COMS technology library. Synthesis results show the delay of the proposed partial product accumulation is reduced by 15.6% and area is reduced by 16.2% comparing with which uses general method. Also, the total delay and area are still reduced despite the delay and area of the CLA are increased.