• Journal of the Korean Society for Precision Engineering
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• v.17 no.5
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• pp.173-179
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• 2000

While a cutting tool is machining a workpiece at various cutting depth, the feedrate is usually selected based on the maximum depth of cut. Even if this selection can avoid power saturation or tool breakage, it is very conservative compared to the capacity of the machine tools and can reduce the productivity significantly. Many adaptive control techniques that can adjust the feedrate to maintain the constant cutting force have been reported. However, these controllers are not very widely used in manufacturing industry because of the limitations in measuring the cutting force signals. In this paper, turning force control systems based on the estimated cutting force signals are proposed. A synthesized cutting force monitor is introduced to estimate the cutting force as accurately as a dynamometer does. Three control strategies of PI, adaptive and fuzzy logic controllers are applied to investigate the feasibility of utilizing the estimated cutting force fur turning force control. The experimental results demonstrate that the proposed systems can be easily realized in CNC lathe with requiring little additional hardware.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2000.04a
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• pp.617-620
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• 2000

In this paper, we show an application of constraint logic programming to the operation scheduling on machines in a job shop. Constraint logic programming is a new genre of programming technique combining the declarative aspect of logic programming with the efficiency of constraint manipulation and solving mechanisms. Due to the latter feature, combinatorial search problems like scheduling may be resolved efficiently. In this study, the jobs that consist of a set of related operations are supposed to be constrained by precedence and resource availability. We also explore how the constraint solving mechanisms can be defined over a scheduling domain. Thus the scheduling approach presented here has two benefits: the flexibility that can be expected from an artificial intelligence tool by simplifying greatly the problem; and the efficiency that stems from the capability of constraint logic programming to manipulate constraints to prune the search space in an a priori manner.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• The KIPS Transactions:PartD
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• v.14D no.1 s.111
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• pp.97-106
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• 2007

In this paper, the business process was easily modeled by distinguishing between the business process and work logic. Based on this model, B2Bi collaboration Workflow modeling tool, which facilitates collaboration, was designed and implemented. The collaboration workflow modeling tool consists of 3 components; business process modeling tool, execution engine and monitoring tool. First, a business process modeling tool is used to build a process map that reflects the business logic of an application in a quick and accurate manner. Second an execution engine provides a real-time execution environment for business process instance. Third, a monitoring tool provides a real-time monitoring function for the business process that is in operation at the time. In addition to this, it supports flexibility and expandability based on XML and J2EE for the linkage with the legacy system that was used previously, and suggests a solution for a new corporate strategy and operation.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1510-1515
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• 2005

This paper is concerned with a Logic-based Fuzzy Neural Networks (LFNN) with the aid of fuzzy granulation. As the underlying design tool guiding the development of the proposed LFNN, we concentrate on the context-based fuzzy clustering which builds information granules in the form of linguistic contexts as well as OR fuzzy neuron which is logic-driven processing unit realizing the composition operations of T-norm and S-norm. The design process comprises several main phases such as (a) defining context fuzzy sets in the output space, (b) completing context-based fuzzy clustering in each context, (c) aggregating OR fuzzy neuron into linguistic models, and (c) optimizing connections linking information granules and fuzzy neurons in the input and output spaces. The experimental examples are tested through two-dimensional nonlinear function. The obtained results reveal that the proposed model yields better performance in comparison with conventional linguistic model and other approaches.

• Journal of the Semiconductor & Display Technology
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• v.5 no.1 s.14
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• pp.33-38
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• 2006

The ATE driver to test a high speed semiconductor chip is designed by using general logic drivers instead of dedicated pin drivers. We have proposed a structure of general logic drivers using FPCA and assured its correct operation by EDA tool simulation. PCB circuit was implemented and Altera FPGA chip was programmed using DDR I/O library. On the PCB, it is necessary to place two resistors connected output drivers near to the output pin to adjust an impedance matching. We confirmed that the measured results agree with the simulated values within 5% errors at room temperature for the input signals with 800Mbps data transfer rate and 1.8V operating voltage.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 1999.10a
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• pp.452-457
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• 1999

The recent control system has been changed into the type of PLC(Programmable Logic Controller) control. Up to now, systematic approach of PLC programming or control logic design is not suggested. In this study, the design process of the control logic is systematized and concrete process in each step is suggested. This systematized approach lead developer to be convenient to implement control system. When some error is occurred in the system, this approach enable the developer to analyze the reason of error rapidly and the system is amended according to systematic information of the analysis. The example of control system implementation following this approach is introduced.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3067-3069
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• 1999

In this paper, A bit processor for controlling sequence logic was implemented, using a FPGA. This processor consists of program memory interface. I/O interface, parts for instruction fetch and decode, registers, ALU, program counter and etc. This FPGA is able to execute sequence instruction during program fetch cycle, because of divided bus system, program bus and data bus. Also this bit processor has instructions set that 16bit or 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package. Finally, the benchmark was performed to prove that Our FPGA has better performance than DSP(TMS320C32-40MHz) for the sequence logic control of PLC.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.1978-1987
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• 2014

Power requirement to the induction heating system varies during the heating process. A closed loop control is required to have a smooth control over the power. In this work, a constant frequency pulse density modulation based power tracking control scheme for domestic induction heating system is developed using the Fuzzy Logic Controller. In the conventional power modulation schemes, the switching losses increase with the change in the load. The proposed pulse density modulation scheme maintains minimum switching losses for the entire load range. This scheme is implemented for the class-D series resonant inverter system. Fuzzy logic controller based power tracking control scheme is developed for domestic induction heating power supply for various power settings. The open loop and closed loop simulation studies are done using the MATLAB/Simulink simulation tool. The control logic is implemented in hardware using the PIC16F877A microcontroller. Fuzzy controller tracks the set power by changing the pulse density of the gate pulses applied to the inverter. The results obtained are used to know the effectiveness of the fuzzy logic controller to achieve the set power.

• The Transactions of the Korea Information Processing Society
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• v.5 no.4
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• pp.995-1004
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• 1998

This paper presents an implementation of model checking tool for LTS process specification, which checks deadlock, livelock and reachability for the state and action. The implemented formal checker using modal mu-calculus is able to verify whether properties expressed in modal logic are true on specifications. We prove experimentally that it is powerful to check, safety and liveness for the state and action on LTS. The tool is implemented by $C^{++}$ language and runs on IBM PC under Windows NT.