• International Journal of Fuzzy Logic and Intelligent Systems
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• v.12 no.1
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• pp.94-100
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• 2012

In this paper, we propose a system which improves text catchphrases on the web using onomatopoeia and the Japanese Google N-grams. Onomatopoeia is regarded as a fundamental tool in daily communication for people. The proposed system inserts an onomatopoetic word into plain text catchphrases. Being based on a large catchphrase encyclopedia, the proposed system evaluates each catchphrase's candidates considering the words, structure and usage of onomatopoeia. That is, candidates are selected whether they contain onomatopoeia and they use specific catchphrase grammatical structures. Subjective experiments show that inserted onomatopoeia is effective for making attractive catchphrases.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.165-168
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• 2001

This paper presents a design of a divide unit supporting IEEE-754 floating point standard single-precision with 32-bit word length. Its functions have been verified with ALTERA MAX PLUS II tool. For a high-speed division operation, the radix-4 non-restoring algorithm has been applied and CLA(carry-look -ahead) adders has been used in order to improve the area efficiency and the speed of performance for the fraction division part. The prevention of the speed decrement of operations due to clocking has been achieved by taking advantage of combinational logic. A quotient select block which is very complicated and significant in the high-radix part was designed by using P-D plot in order to select the fast and accurate quotient. Also, we designed all division steps with Gate-level which visualize the operations and delay time.

• Proceedings of the KIEE Conference
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• 1992.07a
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• pp.51-54
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• 1992

Protection and control systems play a prominent part in avoiding power delivery interruptions and help to get a fast and secure restoration when a failure occurs. In order to meet the higher functional requirements on modern power system, protection speed, selectivity, sensitivity, dependability, and security are essential to ensure reliability. These functions on be satisfied by taking advantage of microprocessor and communication technologies, and digital protection relays (systems) have been developed and applied to real power system enhancing reliability and saving money. It is necessary to have a tool to analyze the functions and algorithms of digital relays for installing them to power system. The purpose of this study is to develop a digital relay simulation program to estimate digital relay performances during system faults. Components of digital protective relay including analog filter, sampling unit, digital filter, and relay logic are modeled in this program.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.5
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• pp.127-136
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• 1989

A Symbolic cover Minimization Algorithm and State CHDL Description for Finite State Machine Synthesizer are Presented. State CHDL are used for design of PLA based finite state machine, also the symbolic cover minimization algorithms are based upon single cube containment and distance 1 merging algorithms. The procedure for state machine synthesizer has been applied to practical example, including traffic light controller by using Boulder Optimal Logic Design System.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.353-356
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• 2002

Due to the increased complexity and size of digital system and the need of the H/W-S/W co-design, C/C++ based system design methodology gains more Interests than ever in EDA field. This paper suggests the methodology in which handshake module corresponding to each basic statement of C is provided of the form of STG(Signal Transition Graph) and then, C statements is synthesized into asynchronous circuit through syntax-oriented translation. The 4-phase handshaking protocol is used for the communications between modules, and the modules are synthesized by the Petrify which is asynchronous logic synthesis CAD tool.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.281-284
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• 2000

This paper describes design of a (32, 28) Reed Solomon decoder for optical compact disk with double error detecting and correcting capability. A variety of error correction codes(ECCs) have been used in magnetic recordings, and optical recordings. Among the various types of ECCs, Reed Solomon(RS) codes has emerged as one the most important ones. The most complex circuit in the RS decoder is the part for finding the error location numbers by solving error location polynomial, and the circuit has great influence on overall decoder complexity. We use RAM based architecture with Euclid's algorithm, Chien search algorithm and Forney algorithm. We have developed VHDL model and peformed logic synthesis using the SYNOPSYS CAD tool. The total umber of gate is about 11,000 gates.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2001.04a
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• pp.202-207
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• 2001

In this paper, it is presented a new technique to the design and real-time implementation of fuzzy control system based-on digital signal processors in order to improve the precision and robustness for system of industrial robot. Fuzzy control has emerged as one of the most active and fruitful areas for research in the applications of fuzzy set theory, especially in the real of industrial processes. In this thesis, a self-organizing fuzzy controller for the industrial robot manipulator with a actuator located at the base is studied. A fuzzy logic composed of linguistic conditional statements is employed by defining the relations of input-output variable of the controller, In the synthesis of a FLC, one of the most difficult problems is the determination of linguistic control rules from the human operators. To overcome this difficult, SOFC is proposed for a hierarchical control structure consisting of basic level and high level that modify control rules.

• 제어로봇시스템학회:학술대회논문집
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• 1995.10a
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• pp.31-34
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• 1995

The automated chemical analysis shop floor are developed for the environmental pollution problems in our chemical analysis center. This shop floor have the several equipments include weight, pour, dry, heater, boiler, mixture, spectroscopy etc. And the material handling components are made up by the stored stack, conveyore, turntables, robot etc. Computer simulation has been an important tool for these complete design problem. We have designed the arangement of chemical equipments and material flow systems by using the simulator "AutoModII". "AutoMoII" is one of the advanced simulator, CAD-like drawing tools with a powerful, engineering oriented language to model control logic and material flow. The result is the modeling of the chemical analysis system in accurate, three dimensional detail. We could designed the set able layout and scheduling system by using the AutoMoII simulator. AutoMoII simulator.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.22-38
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• 1997

This paper proposes a new VLSI architecture for morphological filters and presents its chip design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architecture by using a feedback loop path to reuse partial results and a decoder/encoder pair to detect maximum/minimum values. In addition, the proposed architecture requires one common architecture for both diltion and erosion and fewer number of operations. Moreover, it can be easily extended for larger size morphologica operations. We developed VHDL (VHSIC hardware description language) models, performed logic synthesis using the SYNOPSYS CAD tool. We used the SOG (sea-of-gate) cell library and implemented the actual chip. The total number of gates is only 2,667 and the clock frequency is 30 MHz that meets real-time image processing requirements.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1787-1788
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• 2008

본 논문은 한국원전계측제어시스템(KNICS) 개발 사업의 일환으로 개발되는 안전등급 PLC(Programmable Logic Controller) 소프트웨어 개발 도구의 컴파일러에 대한 시험을 다룬다. 개발된 컴파일러에 대하여 외부 시스템과 연계하지 않고 내부에서 각 컴포넌트 별로 시험하는 컴포넌트 시험과 컴파일러 외부 시스템과 연계하여 시험하는 통합시험을 수행하였다. 시험 과정은 먼저 시험 계획 단계에서 시험 항목을 선정하고 각 항목 별로 사례와 시험 절차를 작성하며 이에 따라 시험을 수행한 결과를 분석하여 컴파일러의 수정 및 보완에 반영하는 것이다.