• Journal of Radiopharmaceuticals and Molecular Probes
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• v.2 no.2
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• pp.103-107
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• 2016

Solid phase extraction (SPE) purification method is the efficient and well-known tool for automated [$^{11}C$]acetate synthesis. A fully automated homemade module adopting the SPE method and 'pinch' valves was developed very economically with a universal interface board, a relay card and an open source programmable logic controller. The radiochemical yield of the optimized [$^{11}C$]acetate synthesis by this system was $58.8{\pm}2.1%$ (n=10, decay-corrected) from $15.5{\pm}0.19GBq$ of $[^{11}C]CO_2$ as starting activity, and total synthetic time was 15 minutes. HPLC analysis showed its high radiochemical purity as $97.4{\pm}1.1%$ without possible by-products.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.849-852
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• 2005

A factorization is an extremely important part of multi-level logic synthesis. The number of literals in a factored from is a good estimate of the complexity of a logic function, and can be translated directly into the number of transistors required for implementation. Factored forms are described as either algebraic or Boolean, according to the trade-off between run-time and optimization. A Boolean factored form contains fewer number of literals than an algebraic factored form. In this paper, we present a new method for a Boolean factorization. The key idea is to identify two-cube Boolean subexpression pairs from given expression. Experimental results on various benchmark circuits show the improvements in literal counts over the algebraic factorization based on Brayton's co-kernel cube matrix.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.400-403
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• 2001

In this paper, the classical Lyapunov synthesis method for designing controllers is extended to fuzzy logic. This control technique is then applied to the design of a novel tracking controller for reluctance motor drives. The main features of the method are small rule base, simplicity of construction, and low cost. The proposed controller has been simulated for a model case. In addition, its dynamic performances have been shown to be satisfactory. Capabilities of the proposed technique in controlling the highly nonlinear systems of reluctance motors with much simplicity are also verified.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.8
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• pp.3715-3722
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• 2011

This paper presents a new Boolean extraction technique for logic synthesis. This method first calculates divisor/2-cube quotients, 2-cube quotient pairs, and 2-cube quotient matrices. Then we find candidates, which can be common sub-expressions, from 2-cube quotients and matrices. Next, candidate intersection provides the common sub-expressions for several logic expressions. Experimental results show the improvements in literal counts over the previous methods.

• Journal of the Korean Society of Industry Convergence
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• v.3 no.1
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• pp.17-27
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• 2000

A factorization is an extremely important part of multi-level logic synthesis. The number of literals in a factored form is a good estimate of the complexity of a logic function. and can be translated directly into the number of transistors required for implementation. Factored forms are described as either algebraic or Boolean, according to the trade-off between run-time and optimization. A Boolean factored form contains fewer number of literals than an algebraic factored form. In this paper, we present a new method for a Boolean factorization. The key idea is to build an extended co-kernel cube matrix using co-kernel/kernel pairs and kernel/kernel pairs together. The extended co-kernel cube matrix makes it possible to yield a Boolean factored form. We also propose a heuristic method for covering of the extended co-kernel cube matrix. Experimental results on various benchmark circuits show the improvements in literal counts over the algebraic factorization based on Brayton's co-kernel cube matrix.

• Journal of the Korea Computer Industry Society
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• v.7 no.4
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• pp.293-298
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• 2006

A factorization is an extremely important part of multi-level logic synthesis. The number of literals in a factored form is a good estimate of the complexity of a logic function, and can be translated directly into the number of transistors required for implementation. Factored forms are described as either algebraic or Boolean, according to the trade-off between run-time and optimization. A Boolean factored form contains fewer number of literals than an algebraic factored form. In this paper, we present a new method for a Boolean factorization. The key idea is to identify two-cube Boolean subexpression pairs from given expression. Experimental results on various benchmark circuits show the improvements in literal counts over the algebraic factorization based on Bryton's co-kernel cube matrix.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.11
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• pp.2365-2374
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• 1997

This paper describes two algorithms for technology mapping of multiple output functions into interesting and pupular FPGAs(Field Programmable Gate Array) that use look-yp table memories. For improvement of technology mapping for FPGA, we use the functional decompoition method for multiple output functions. Two algorithms are proposed. The one is the Roth-Karpalgorithm extended for multiple output functions. The other is the efficient algorithm which looks for common decomposition functions through the decomposition procedure. The cost function is used to minimize the number of CLBs and nets and to improve performance of the network. Finally we compare our new algorithm with previous logic design technique. Experimental resutls show sigificant reduction in the number of CLBs and nets.

• Journal of Institute of Control, Robotics and Systems
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• v.8 no.8
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• pp.706-712
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• 2002

In general, a deadlock in flexible manufacturing systems (FMSs) is caused by a resource limitation and the diversity of routings. However, the deadlock of industrial controllers such as programmable logic controllers (PLCs) can occur from different causes compared with those in general FMSs. The deadlock of PLCs is usually caused by an error signal between PLCs and manufacturing systems. In this paper, we propose a deadlock detection and recovery (DDR) algorithm to resolve the deadlock problem of PLCs at design stage. This paper employs the MAPN (modified automation Petri net), MTPL (modified token passing logic), and ECC (efficient code conversion) algorithm to model manufacturing systems and to convert a Petri net model into a desired LD (ladder diagram). Finally, an example of manufacturing systems is provided to illustrate the proposed DDR algorithm.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.875-878
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• 1998

In this thesis, we present efficient techniques to reduce the switching activity in a CMOS combinational logic network based on local logic transforms. But this techniques is not appropriate in the view of testability because of deteriorating the random pattern testability of a circuit. This thesis proposes a circuit design method having two operation modes. For the sake of power dissipation(normal operation mode), a gate output switches as rarely as possible, implying highly skewed signal probabilities for 1 or 0. On the other hand, at test mode, signals have probabilities of being 1 or 0 approaching 0.5, so it is possible to exact both stuck-at faults on the wire. Therefore, the goals of synthesis for low power and random pattern testability are achieved. The hardware overhead sof proposed design method are only one primary input for mode selection and AND/OR gate for each redundant connection.

• Journal of Electrical Engineering and information Science
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• v.3 no.1
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• pp.8-13
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• 1998

Often ESOP(Exclusive Sum of Products) expressions provide more compact representations of logic functions and implemented circuits are known to be highly testable. Motivated by the merits of using XOR(Exclusive-OR) gates in circuit design, ESOP(Exclusive Sum of Products) expressions are considered s the input to the logic synthesis for random pattern testability. The problem of interest in this paper is whether ESOP expressions provide better random testability than corresponding SOP expressions of the given function. Since XOR gates are used to collect product terms of ESOP expression, fault propagation is not affected by any other product terms in the ESOP expression. Therefore the test set for a fault in ESOP expressions becomes larger than that of SOP expressions, thereby providing better random testability. Experimental results show that in many cases, ESOP expressions require much less random patterns compared to SOP expressions.