• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.3
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• pp.571-578
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• 2012

In this paper, we propose two main points. The first is the constraint for logic synthesis, and the second is an efficient logic synthesis method. Logic synthesis is a process to obtain the gate-level netlist from RTL (register transfer level) codes using logic mapping and optimization with the specified constraints. The result of logic synthesis is tightly dependent on constraint and logic synthesis method. Since the size and timing can be dramatically changed by these, we should precisely consider them. In this paper, we present the considering items in the process of logic synthesis by using our experience and experimental results. The proposed techniques was applied to a circuit with the hardware resource of about 650K gates. The synthesis time for the hybrid method was reduced by 47% comparing the bottom-up method and It has better timing property about slack than top-down method.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.9
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• pp.5744-5749
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• 2014

An extraction technique for a common logic expression is an extremely important part of multiple-output logic synthesis. This paper presents a new Boolean extraction technique using an exclusive-OR logic synthesis principle. The logic circuits produced only have AND, OR and NOT gates. Heuristic methods can also be applied to reduce the execution time and the number of literals. The experimental results showed improvements in the literal counts over the previous methods.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.11
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• pp.94-104
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• 1995

In this paper, we present a new multi-level logic synthesis method for producing the multi-level circuits which can be easily tested by the pseudoexhaustive testing techniques. The method consists of four stages. In the first stage, it generates the minimum variable supports for each output of a multiple-output function. In the second stage, it removes the minimum variable supports which if used to implement the outputs, lead to inefficient pseudoexhaustive test. In the third stage, it determines the minimum variable support and logic (uncomplementary or complementary logic) for each output. In the fourth stage, it performs the multi-level logic synthesis so that each output. In the fourth stage, it performs the multi-level logic synthesis so that each output has the minimum variable support and logic determined in the third stage. To evaluate the performance and quality of the proposed method, we have experimented on the 56 benchmark examples. The results show that for 56 examples, our method obtains better results than MIS in terms of testability. Moreover, the method produces better results for 19 examples and the same results for 12 examples compared with MIS in terms of literal count although it has been developed to improve the testability.

• Journal of Korea Multimedia Society
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• v.11 no.12
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• pp.1739-1748
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• 2008

When we conduct a data mining procedure on sample data sources, several rules are generated. But some rules are redundant or logically disjoint and therefore they can be removed. We suggest a new rule minimization algorithm inspired from logic synthesis to improve comprehensibility and eliminate redundant rules. The method can merge several relevant rules into one based on data mining and logic synthesis without high loss of accuracy. In case of two or more rules are candidates to be merged, we merge the rules with the attribute having the lowest information gain. To show the proposed method could be a reasonable solution, we applied the proposed approach to a problem domain constructing user preferred ontology in anti-spam systems.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.1
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• pp.74-84
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• 1991

This paper presents an algorithm for technology-dependent logic optimization and technology mapping, and describes a performance-driven logic synthesis system, SILOS, implemented based on the proposed algorithm. The system analyzes circuits and resynthesizes the critical sections such that generated circuit operates opertes within time constraints, using only gate types supported by library for direct implementation. Experimental results show that the system can be a viable tool in synthesizing high-performance logic circuits.

• Journal of the Korean Institute of Gas
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• v.5 no.1
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• pp.37-44
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• 2001

OPS(Operating Procedure Synthesis) systems can reduce the time and effort involved in OPS, make the analysis more thorough and detailed, and minimize or eliminate human errors. And OPS systems capture the expertise needed to create operating procedures and allow this experience to be used in the new situations. But there are the limitations of the OPS techniques that have been used. So in order to resolve this Problem, in this work we have proposed a new approach to utilize temporal constraints and specific process knowledge in temporal logic and description logic. We have demonstrated its remarkable effectiveness in a boiler plant.

• The Journal of Korean Association of Computer Education
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• v.15 no.1
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• pp.65-72
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• 2012

Generally, a logic function has many factored forms. The problem of finding more compact factored form is one of the basic operations in logic synthesis. In this paper, we present a new method for factoring Boolean functions to assist in educational logic designs. Our method for factorization is to implement two-cube Boolean division with supports of an expression. The number of literals in a factored form is a good estimate of the complexity of a logic function. Our empirical evaluation shows the improvements in literal counts over previous other factorization methods.

• The Transactions of the Korea Information Processing Society
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• v.3 no.3
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• pp.564-571
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• 1996

The logic synthesis systems for table look up(TLU) type field programmable e gate arrays(FPGAs) have so farstudied mostly the combinational logic problem m. This paper presents for mapping a sequential circuit onto a popular table look up architecture, theXilinx 3090 architecture. In thefirst for solving this problem, combinational and sequential elements which have 6 or7 input combinational and sequential elements which haveless thanor equal to 5 inputs. We heavily use the combinational synthesis techniques tosolve the sequential synthesis problem. Our syntheisis approach is very simple, but its results are reasonable. We compare seveal benchmark Examples with sis-pga(map_together and map_separate) synthesis system and the experimental results show that our synthesis system is 17% betterthan sis-pga sequential synthesis system for TLU PGAs.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.337-340
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• 2000

In this paper, we put forth a procedure that target low power logic synthesis based on XOR representation of Boolean functions, and the results of synthesis procedure are a multi-level XOR form with minimum switching activity. Specialty, this paper show a method to extract the common cubes or kernels by Boolean matrix and rectangle covering, and to estimate the power consumption in terms of the extracted common sub-functions.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.1
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• pp.57-63
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• 1994

The logic function synthesis using ULM U$_h$ is constructed based on canonic Reed-Muller expansion coefficient for a given function. This paper proposes the fast synthesis algorithm using ULM U$_h$ for ternary function. By using circuit cost and synthesis method of proposed in this paper, order of control input variable minimum number of ULM U$_h$ can be decided in the synthesis of n-variable ternary function. Accordingly, this method enables to optimum circuit realization for ternary function synthesis using ULM ULM U$_h$ and can be applied to ternary function synthesis using ULM U$_h$. The complexity of search for select the order of all control input variables is (n+2)(n-1)/2.