• Journal of Power Electronics
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• v.14 no.6
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• pp.1303-1313
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• 2014

Dynamic behavior of the harmonic detection part of an active power filter (APF) has an essential role in filter compensation performances during transient conditions. Instantaneous power (p-q) theory is extensively used to design harmonic detectors for active filters. Large overshoot of p-q theory method deteriorates filter response at a large and rapid load change. In this study the harmonic estimation of an APF during transient conditions for balanced three-phase nonlinear loads is conducted. A novel fuzzy instantaneous power (FIP) theory is proposed to improve conventional p-q theory dynamic performances during transient conditions to adapt automatically to any random and rapid nonlinear load change. Adding fuzzy rules in p-q theory improves the decomposition of the alternating current components of active and reactive power signals and develops correct reference during rapid and random current variation. Modifying p-q theory internal high-pass filter performance using fuzzy rules without any drawback is a prospect. In the simulated system using MATLAB/SIMULINK, the shunt active filter is connected to a rapidly time-varying nonlinear load. The harmonic detection parts of the shunt active filter are developed for FIP theory-based and p-q theory-based algorithms. The harmonic detector hardware is also developed using the TMS320F28335 digital signal processor and connected to a laboratory nonlinear load. The software is developed for FIP theory-based and p-q theory-based algorithms. The simulation and experimental tests results verify the ability of the new technique in harmonic detection of rapid changing nonlinear loads.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11A
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• pp.1271-1277
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• 2004

We propose a foe phase tuner and a rounding processor for a numerically controlled oscillator (NCO), yielding a reduced phase error in generating a digital sine waveform. By using the fine Phase tuner Presented in this paper, when the ratio of the desired sine wave frequency to the clock frequency is expressed as a fraction, an accurate adjustment in representing the fractional value can be achieved with simple hardware. In addition, the proposed rounding processor reduces the effects of phase truncation on the output spectrum. Logic simulation results of the NCO for multi-carrier channel separation in cdma2000 3X multi-carrier receive system using these techniques show that the noise spectrum and mean square error (MSE) are reduced by 8.68 dB and 5.5 dB, respectively compared to those of truncation method and 2.38 dB and 0.83 dB, respectively, compared to those of Paul's scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.8B
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• pp.646-656
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• 2008

In this paper, we design and verify the MAC chip of the two-stage AWG-based WDM-PON which considers 128 ONUs and 32 wavelengths. Each wavelength with the capacity of 1Gbps is allocated to ONU for downstream transmission but each wavelength for upstream transmission can be shared by four ONUs. Therefore, MAC protocol is required to avoid the collision and use the network resource efficiently among ONUs which are sharing the same wavelength. To design a request/permit-based MAC protocol, we define a unit-chip module called sub-MAC. The WDM-PON with 128 ONUs can be implemented by using 32 sub-MAC modules. The sub-MAC consists of one control unit, one receipt unit and four transmission units. The state transition diagram of the module is described by the internal/external control signals among the functional units. The function of the sub-MAC module is verified through logic simulation using ModelSIM.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.38 no.3
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• pp.228-235
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• 2010

This paper deals with an autonomous flight controller design problem for a tilt-rotor aircraft in rotary-wing mode. The inner-loop algorithm is designed using the output-based approximate feedback linearization. The model error originated from the feedback linearization is cancelled within allowable tolerance by using single-hidden-layer neural network. According to Lyapunov direct stability theory, the adaptive update law is derived to run the neural network on-line, which is based on the linear observer dynamics. Moreover, the outer-loop algorithm is designed to track the trajectory generated from way-point guidance. Especially, heading and flight-path angle line-of-sight guidance are applied to the outer-loop to improve accuracy of the landing tracking performance. The 6-DOF nonlinear simulation shows that the overall performance of the flight control algorithm is satisfactory even though the collective input response shows instantaneous actuator saturation for a short time due to the lack of the neural network and the saturation protection logic in that loop.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.2
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• pp.78-84
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• 2000

The Viterbi decoders can be classified into serial Viterbi decoders and parallel Viterbi decoders. Parallel Viterbi decoders can handle higher data rates than serial Viterbl decoders. This paper designs and implements a fully parallel Viterbi decoder for high speed multimedia communications. For high speed operations, the ACS (Add-Compare-Select) module consisting of 64 PEs (Processing Elements) can compute one stage in a clock. In addition, the systolic away structure with 32 pipeline stages is developed for the TB (traceback) module. The implemented Viterbi decoder can support code rates 1/2, 2/3, 3/4, 5/6 and 7/8 using punctured codes. We have developed Verilog HDL models and performed logic synthesis. The 0.6 ${\mu}{\textrm}{m}$ SAMSUNG KG75000 SOG cell library has been used. The implemented Viterbi decoder has about 100,400 gates, and is running at 70 MHz in the worst case simulation.

• The Journal of the Acoustical Society of Korea
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• v.18 no.2
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• pp.53-60
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• 1999

In this paper, it is proposed to a new architecture of CMOS IADC(Current-Mode Analog-to-Digital Converter) using 1.5-bit bit cell of which consists a CSH(Current-Mode Sample-and-Hold) and CCMP(Current-Mode Comparator). In order to guarantee the entire linearity of IADC, the CSH is designed to cancel CFT(Clock Feedthrough) whose resolution is to meet at the least 9-bit which is placed in the front-end of each bit cell. In the proposed IADC, digital correction logic is simplified and power consumption is reduced because bit cell of each stage needs two latch CCMP. Also, it is available for a mixed-mode integrated circuit because all of block is designed with only MOS transistor. With the HYUNDAI 0.8㎛ CMOS parameter, the HSPICE simulation results show that the proposed IADC can be operated at 20Ms/s with SNR of 43 dB with which is satisfied 7-bit resolution for input signal at 100 ㎑, and its power consumption is 27㎽.

• Journal of the Korea Society of Computer and Information
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• v.12 no.6
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• pp.167-175
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• 2007

Fuzzy logic is used to represent qualitative knowledge and provides interpretability to a controlling system model in bioinformatics. This paper focuses on a bioinformatics data classification which is an important bioinformatics application. This paper reviews the two traditional controlling system models The sequence-based threshold controller have problems of optimal range decision for threshold readjustment and long processing time for optimal threshold induction. And the binary-based threshold controller does not guarantee for early system stability in the GPCR data classification for optimal threshold induction. To solve these problems, we proposes a fuzzy-based threshold controller for ART1 clustering in GPCR classification. We implement the proposed method and measure processing time by changing an induction recognition success rate and a classification threshold value. And, we compares the proposed method with the sequence-based threshold controller and the binary-based threshold controller The fuzzy-based threshold controller continuously readjusts threshold values with membership function of the previous recognition success rate. The fuzzy-based threshold controller keeps system stability and improves classification system efficiency in GPCR classification.

• Journal of the Earthquake Engineering Society of Korea
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• v.9 no.4 s.44
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• pp.55-66
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• 2005

The effectiveness of fuzzy supervisory control technique for the control of seismic responses of smart base isolation system is investigated in this study. To this end, first generation base isolated building benchmark problem is employed for the numerical simulation. The benchmark structure under consideration is an eight-story base isolated building having irregular plan and is equipped with low-damping elastometric bearings and magnetorheological (MR) dampers for seismic protection. Lower level fuzzy logic controllers (FLC) for far-fault or near-fault earthquakes are developed in order to effectively control base isolated building using multi-objective genetic algorithm. Four objectives, i.e. reduction of peak structural acceleration, peak base drift, RMS structural acceleration and RMS base drift, are used in multi-objective optimization process. When earthquakes are applied to benchmark building, each of low level FLCs provides different command voltage and supervisory fuzzy controller combines two command voltages io one based on fuzzy inference system in real time. Results from the numerical simulations demonstrate that base drift as well as superstructure responses can be effectively reduced using the proposed supervisory fuzzy control technique.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.1
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• pp.46-56
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• 1991

In this paper, 16word X 8bit Content Addressable and Reentrant Memory(CARM) is described. This device has 4 operation modes(read, write, match, reentrant). The read and write operation of CARM is like that of static RAM, CARM has the reentrant mode operation where the on chip garbage collection is accomplished conditionally. Thus function can be used for high speed matching unit of dynamic data flow computer. And CARM also can encode matching address sequentially according to therir priority. CARM consists of 8 blocks(CAM cell, Sequential Address Encoder(S.A.E). Reentrant operation. Read/Write control circuit, Data/Mask Register, Sense Amplifier, Encoder. Decoder). Designed DARM can be used in data flow computer, pattern, inspection, table look-up, image processing. The simulation is performed using the QUICKSIM logic simulator and Pspice circuit simulator. Having hierarchical structure, the layout was done using the 3{\;}\mu\textrm{m} n well CMOS technology of the ETRI design rule.

• Journal of the Korean Institute of Intelligent Systems
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• v.8 no.2
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• pp.70-81
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• 1998

This paper proposes an accurate and cost-effective COA defuzzifier of fuzzy logic controller (FLC). The accuracy of the proposed COA defuzzifier is obtained by involving both membership values and spans of membership functions in calculating a crisp value. The cost-effectiveness of the proposed COA defuzzifier is obtained by replacing the division in the COA defuzzifier by finding an equilibrium point of both the left and right moments. The proposed COA defuzzifier has two disadvantages that it ncreases the hardware complexity due to the additional multipliers and it takes a lot of computation time to find the moment equilibrium point. The first disadvantage is overcome by replacing the multipliers with the stochastic AND operations. The second disadvantage is alleviated by using a coarse-to-fine searching algorithm that accelerates the finding of moment equilibrium point. Application of the proposed COA defuzzifier to the truck backer-upper control problem is performed in the VHDL simulation and the control accuracy of the proposed COA defuzzifier is compared with that of the conventional COA defuzzifier in terms of average tracing distance.