• Journal of the Korean Institute of Intelligent Systems
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• v.10 no.2
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• pp.152-160
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• 2000

This paper addresses the analysis and design of fuzzy-model-based controller for nonlinear systems using extended PDC and optimal pole-placement schemes. In the design procedure, we represent the nonlinear system using a Takagi-Sugeno fkzy model and formulate the controller rules by using the extended parallel distributed compensator (EPDC) and construct an overall fuzzy logic controller by blending all local state feedback controllers with an optimal pole-placement scheme. Unlike the commonly used parallel distributed compensation technique, by blending a newly extended parallel distributed compensator and the optimal poleplacement schemes, we can design not only a local stable k z y controller but also an overall stable fuzzy controller to perform the tacking control objective. Furthermore, a stability analysis is carried out not only for the fuzzy model but also for a real nonlinear system. Finally. the effectiveness and feasibility of the proposed fizzy model-based controller design method has been shown through a simulation example.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.11 no.4
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• pp.217-222
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• 2011

Genetic algorithms are one of the most important methods used to solve the Traveling Salesman Problem. Therefore, many researchers have tried to improve the Genetic Algorithm by using different methods and operations in order to find the optimal solution within reasonable time. This paper intends to find a new approach that adopts an improved genetic algorithm to solve the Traveling Salesman Problem, and compare with the well known heuristic method, namely, Kohonen Self-Organizing Map by using different data sets of symmetric TSP from TSPLIB. In order to improve the search process for the optimal solution, the proposed approach consists of three strategies: two separate tour segments sets, the improved crossover operator, and the improved mutation operator. The two separate tour segments sets are construction heuristic which produces tour of the first generation with low cost. The improved crossover operator finds the candidate fine tour segments in parents and preserves them for descendants. The mutation operator is an operator which can optimize a chromosome with mutation successfully by altering the mutation probability dynamically. The two improved operators can be used to avoid the premature convergence. Simulation experiments are executed to investigate the quality of the solution and convergence speed by using a representative set of test problems taken from TSPLIB. The results of a comparison between the new approach using the improved genetic algorithm and the Kohonen Self-Organizing Map show that the new approach yields better results for problems up to 200 cities.

• The KIPS Transactions:PartC
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• v.8C no.1
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• pp.32-40
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• 2001

In this paper, we propose a high-speed modular multiplication algorithm which revises conventional Montgomery's algorithm. A hardware architecture is also presented to implement 1024-bit RSA cryptosystem for digital signature based on the proposed algorithm. Each iteration in our approach requires only one addition operation for two n-bit integers, while that in Montgomery's requires two addition operations for three n-bit integers. The system which is modelled in VHDL(VHSIC Hardware Description Language) is simulated in functionally through the use of $Synopsys^{TM}$ tools on a Axil-320 workstation, where Altera 10K libraries are used for logic synthesis. For FPGA implementation, timing simulation is also performed through the use of Altera MAX + PLUS II. Experimental results show that the proposed RSA cryptosystem has distinctive features that not only computation speed is faster but also hardware area is drastically reduced compared to conventional approach.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.38 no.9
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• pp.882-889
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• 2010

Semi-active vibration control is one of the attractive control methods for space application due to its robustness as passive damping system and much higher damping performance than passive system. However, a chattering induced by the sudden variation of damping force at the time of On-Off switching of semi-active control device degrades pointing performance of the on-board payload. In this paper, to enhance the pointing performance of the on-board payload, we proposed a semi-active vibration isolation with a strategy for attenuating chattering effect. Numerical simulation results using simplified analysis model indicated that the proposed semi-active control strategy produced much better isolation performance than the conventional Bang-Bang control semi-active control laws derived from skyhook and LQ theories.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1349-1359
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• 1998

In this paper, presented is the result of a digital implementation of a FM stereo composite signal generator. The chip utilizing DDFS(Direct Digital Frequency Synthesizer architecture is implemented using $1.0\mu\textrm{m}$ CMOS gate-array technology thereby replacing analog componentry. To verify the process of generating composite signals a conventional logic simulation method was used. The processed chip was mounted on an evaluation PCB to test and analyze to signals. According to the measurement result obtained by using a 12-bit DAC, the digital FM composite signal generator produces a 74DB spectrally pure signal over its entire tuning range, which is superior to that of analog counterpart by 14dB in it spectral reponse. And further enhancements of the spectral response is expected to be achieved by using a high resolution digital to analog converter, such as a 16-bit DAC. The resulting signals is superior to the signal of the analoy circuitry typically used, in major characteristics such as S/N ratios, accuracy, tuning stability, and signal seperation.

• The Transactions of the Korea Information Processing Society
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• v.5 no.9
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• pp.2378-2387
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• 1998

This thesis proposes a design algorithm of an efficient space response compactor for Built-In Self-Testing of VLSI circuits. The proposed design algorithm of space compactors can be applied independently from the structure of Circuit Cnder Test. There are high hardware overhead cost in conventional space response compactors and the fault coverage is reduced by aliasing which maps faulty circuit's response to fault-free one. However, the proposed method designs space response compactors with reduced hardware overheads and does not reduce the fault coverage comparing to conventional method. Also, the proposed method can be extended to general N -input logic gate and design the most efficient space response L'Ompactors according to the characteristies of output sequence from CUT. The prolxlsed design algorithm is implemented by C language on a SUN SPARC Workstation, and some experiment results of the simulation applied to ISCAS'85 benchmark circuits with pseudo random patterns generated bv LFSR( Linear Feedback Shift Register) show the efficiency and validity of the proposed design algorithm.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.5
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• pp.74-82
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• 2004

This paper describes the speed control of the surface-mounted permanent-magent synchronous motors (SMPMSNM) for elevator drive. The elevator motor needs to be a compact and slim type. Essentially, the proposed scheme uses a vector control algorithm for a speed and torque control and Anti-windup technique is adopted to prevent a windup phenomenon. This system is implemented using a high speed 32-bit DSP (TMS320C31-50), a high-integrated logic device FPGA(EPF10K10TI144-3) to design compactly and inexpensively. The proposed scheme is verified by the results through digital simulation and experiments for a three-phase 13.3[kW] SMPMSM as a MRL(MachineRoomLess) elevator motor in the laboratory.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.11
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• pp.80-87
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• 2005

T-50 supersonic jet trainer aircraft using digital flight-by-wire flight control system receives aircraft flight conditions such as altitude, VCAS(Calibrated Airspeed) and Angle of Attack from IMFP(Integrated Multi-Function Probe). IMFP sensors information have triplex structure using three IMFP sensors. Air-data selection logic is mid-value selection in three information from three IMFP sensors in order to have more reliability. From supersonic flight test at high altitude, air-data information is dropped simultaneously because of supersonic shock wave effect. This error information may affect to aircraft stability and safety in supersonic area at low altitude. This paper propose that sensitivity analysis and HQS(Handling Quality Simulator) pilot simulation in order to analyze flight stability and controllability in supersonic area at low altitude when these information is applied to flight control law.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.5
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• pp.65-73
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• 2006

When a satellite separates from the launch vehicle, an initial high angular rate or a tip-off rate is generated. B-dot logic is generally used for controlling the initial tip-off rate. However, it has the disadvantage of taking a relatively long time to control the initial tip-off rate. To solve this problem, this paper suggests a new detumbling control method to be able to adapt to micro/nanosatellite with the pitch bias momentum system. Proposed detumbling method was able to control the angular rate within 20 minutes which is significantly reduced compared to conventional methods. Since the previous wheel start-up method cannot be used if the detumbling controller proposed by this paper is used, a method is also proposed for bringing up the momentum wheel speed to nominal rpm while maintaining stability in this paper. The performance of the method is compared and verified through simulation. The overall result shows much faster control time compared to the conventional methods, and achievement of the nominal wheel speed and 3-axes stabilization while maintaining stability.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.5
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• pp.1143-1150
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• 2000

A dual-mode multiplier (DMM) that performs single- and double-precision multiplications has been designed using a $0.25-\mum$ 5-metal CMOS technology. An algorithm for efficiently implementing double-precision multiplication with a single-precision multiplier was proposed, which is based on partitioning double-precision multiplication into four single-precision sub-multiplications and computing them with sequential accumulations. When compared with conventional double-precision multipliers, our approach reduces the hardware complexity by about one third resulting in small silicon area and low-power dissipation at the expense of increased latency and throughput cycles. The DMM consists of a $28-b\times28-b$ single-precision multiplier designed using radix-4 Booth receding and redundant binary (RB) arithmetic, an accumulator and a simple control logic for mode selection. It contains about 25,000 transistors on the area of about $0.77\times0.40-m^2$. The HSPICE simulation results show that the DMM core can safely operate with 200-MHZ clock at 2.5-V, and its estimated power dissipation is about 130-㎽ at double-precision mode.