• Journal of Institute of Control, Robotics and Systems
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• v.11 no.3
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• pp.254-261
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• 2005

Time-optimal performances are analyzed in the sense of inner loop. A varying-time sharing thrusting logic is suggested as a new sequential paired thrusting logic for fast maneuvers of satellites with coupled thruster configuration. Its time-optimal maneuvering performance is compared with two conventional thrusting logics: separate thrusting logic and constant-time sharing sequential paired thrusting logic. It is found that the newly suggested varying-time sharing thrusting logic can be easily implemented by adjusting the conventional constant-time logic with its thrust on-time, while it can reduce the maneuvering time enormously as much as the separate thrusting logic. The performance of the logic is simulated on the agile maneuvering spacecraft model KOMPSAT-II.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.118-127
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• 2015

This paper presents an advanced torque ripple minimization method of a switched reluctance motor (SRM) using torque sharing function (TSF). Generally, TSF is applied into the torque control. However, the conventional TSF cannot follow the expected torque well because of the nonlinear characteristics of the SRM. Moreover, the tail current that is generated at a high speed motor drive makes unexpected torque ripples. The proposed method combined TSF with fuzzy logic control (FLC). The advantage of this method is that the torque can be controlled unity at any conditions. In addition, the controller can track the torque under the condition of the wrong TSF. The effectiveness of the proposed algorithm is verified by the simulations and experiments.

• Journal of Mechanical Science and Technology
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• v.19 no.9
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• pp.1695-1705
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• 2005

Reaction wheels and thrusters are commonly used for the satellite attitude control. Since satellites frequently need fast maneuvers, the minimum time maneuvers have been extensively studied. When the speed of attitude maneuver is restricted due to the wheel torque capacity of low level, the combinational use of wheel and thruster is considered. In this paper, minimum time optimal control performances with reaction wheels and thrusters are studied. We first identify the features of the maneuvers of the satellite with reaction wheels only. It is shown that the time-optimal maneuver for the satellite with four reaction wheels in a pyramid configuration occurs on the fashion of single axis rotation. Pseudo control logic for reaction wheels is successfully adopted for smooth and chattering-free time-optimal maneuvers. Secondly, two different thrusting logics for satellite time-optimal attitude maneuver are compared with each other: constant time-sharing thrusting logic and varying time-sharing thrusting logic. The newly suggested varying time-sharing thrusting logic is found to reduce the maneuvering time dramatically. Finally, the hybrid control with reaction wheels and thrusters are considered. The simulation results show that the simultaneous actuation of reaction wheels and thrusters with varying time-sharing logic reduces the maneuvering time enormously. Spacecraft model is Korea Multi-Purpose Satellite (KOMPSAT)-2 which is being developed in Korea as an agile maneuvering satellite.

• ETRI Journal
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• v.26 no.6
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• pp.545-554
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• 2004

In this paper, we propose an efficient design method for area optimization in a digital filter. The conventional methods to reduce the number of adders in a filter have the problem of a long critical path delay caused by the deep logic depth of the filter due to adder sharing. Furthermore, there is such a disadvantage that they use the transposed direct form (TDF) filter which needs more registers than those of the direct form (DF) filter. In this paper, we present a hybrid structure of a TDF and DF based on the flattened coefficients method so that it can reduce the number of flip-flops and full-adders without additional critical path delay. We also propose a resource sharing method and sharing-pattern searching algorithm to reduce the number of adders without deepening the logic depth. Simulation results show that the proposed structure can save the number of adders and registers by 22 and 26%, respectively, compared to the best one used in the past.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.181-186
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• 2005

In collaborative environment, it is necessary that the participants in collaboration should share the same understanding about the semantics of terms. For example, they should know that 'Part' and 'Item' are different word-expressions for the same meaning. In this paper, we consider sharing between CAD and PDM data. In order to handle such problems in information sharing, an information system needs to automatically recognize that the terms have the same semantics. Serving this purpose, the semantic mapping logic and the ontology based mapper system is described in this paper. In the semantic mapping logic topic, we introduce our logic that consists of four modules: Character Matching, Instance Reasoning, definition comparing and Similarity Checking. In the ontology based mapper, we introduce the system architecture and the mapping procedure.

• Journal of the Optical Society of Korea
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• v.18 no.5
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• pp.477-484
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• 2014

In this paper, we propose a new optical secret key sharing method based on the Diffie-Hellman key exchange protocol required in cipher system. The proposed method is optically implemented by using a free-space interconnected optical logic gate technique in order to process XOR logic operations in parallel. Also, we present a compact type of optical module which can perform the modified Diffie-Hellman key exchange for a cryptographic system. Schematically, the proposed optical configuration has an advantage of producing an open public key and a shared secret key simultaneously. Another advantage is that our proposed key exchange system uses a similarity to double key encryption techniques to enhance security strength. This can provide a higher security cryptosystem than the conventional Diffie-Hellman key exchange protocol due to the complexity of the shared secret key. Results of numerical simulation are presented to verify the proposed method and show the effectiveness in the modified Diffie-Hellman key exchange system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.331-340
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• 2012

In the deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. Spare columns are often included in memories to repair defective cells or bit lines during production test. In many cases, the repair process will not use all spare columns. Schemes have been proposed to exploit these unused spare columns to store additional check bits which can be used to reduce the miscorrection probability for triple errors in single error correction-double error detection (SEC-DED). These additional check bits increase the dimensions of the parity check matrix (H-matrix) requiring extra area overhead. A method is proposed in this paper to efficiently fill the extra rows of the H-matrix on the basis of similarity of logic between the other rows. Optimization of the whole H-matrix is accomplished through logic sharing within a feasible operating time resulting in reduced area overhead. A detailed implementation using fuse technology is also proposed in this paper.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1221-1224
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• 2003

A 64-point R2$^2$ SDF pipeline FFT processor using a new efficient computation sharing multiplier was designed. Computation sharing multiplication specifically targets computation re-use in multiplication of coefficient vector by scalar and is effectively used in DSP(Digital Signal Processing). To reduce the number of multipliers in FFT, we used the proposed computation sharing multiplier. The 64-point pipeline FFT processor was implemented by VHDL and synthesized using Max+PLUSII of Altera. The simulation result shows that the proposed computation sharing multiplier can be reduced to about 17.8% logic cells compared with a conventional multiplier. This processor can operate at 33MHz and calculate a 64-point pipeline FFT in 1.94 $mutextrm{s}$.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.115-117
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• 2019

In this paper, an intelligent control scheme based on Fuzzy PID controller is proposed for accurate power sharing in DC Microgrid. The proposed Fuzzy PID controller is designed with the aid of a closed loop control based on per unit power of each distributed generator (DG), and accurate power sharing is successfully realized in proportional to each DG's power rating regardless of the line resistance difference or the load change. Thanks to Fuzzy PID controller, the dynamic response becomes faster and the stability of the microgrid system are improved in comparison to conventional PID controller. The superiority of the proposed method is analyzed and verified by simulation in Matlab and Simulink.

• Smart Structures and Systems
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• v.14 no.6
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• pp.1131-1150
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• 2014

One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.