• 조명전기설비학회논문지
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• 제14권1호
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• pp.59-66
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• 2000

최근 산업공정 시스댐이 복잡해지고 고도의 성능을 요구함에 따라 PLC의 하드혜어와 소프트웨어의 성능이 향상되었다. SFC 그래픽 언어는 순차 논리 알고리즘을 기술뿐만 아니라 인터록 제어 알고리즘과 같은 에러 관리 알고리즘을 기술하는 데에도 적합하다. 본 논문에서는 산업 공정 제어 시스템을 기술하는데 있어서 효과적으로 에러를 관리하기 위해 제한자를 이용 한 에러 관리 방법올 제안하였으며, 제안된 방법으로 필름 코탱기 제어 시스템을 구현한 결과 에러 관리가 용이하고 프로그랩 메모리의 용량을 줄일 수 있었음을 확인하였다.

• 품질경영학회지
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• 제11권2호
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• pp.2-9
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• 1983

As will be seen, this paper is tries that the research on the mathematical structure of Markov process and Markovian sequential decision process (the policy improvement iteration method,) moreover, that it analyze the logic and the characteristic of behavior of mathematical model of Markov process. Therefore firstly, it classify, on research of mathematical structure of Markov process, the forward equation and backward equation of Chapman-kolmogorov equation and of kolmogorov differential equation, and then have survey on logic of equation systems or on the question of uniqueness and existence of solution of the equation. Secondly, it classify, at the Markovian sequential decision process, the case of discrete time parameter and the continuous time parameter, and then it explore the logic system of characteristic of the behavior, the value determination operation and the policy improvement routine.

• Nuclear Engineering and Technology
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• 제44권6호
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• pp.697-708
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• 2012

The majority of instrumentation and control (I&C) systems in today's nuclear power plants (NPPs) are based on analog technology. Thus, most existing I&C systems now face obsolescence problems. Existing NPPs have difficulty in repairing and replacing devices and boards during maintenance because manufacturers no longer produce the analog devices and boards used in the implemented I&C systems. Therefore, existing NPPs are replacing the obsolete analog I&C systems with advanced digital systems. New NPPs are also adopting digital I&C systems because the economic efficiencies and usability of the systems are higher than the analog I&C systems. Digital I&C systems are based on two technologies: a microprocessor based system in which software programs manage the required functions and a programmable logic device (PLD) based system in which programmable logic devices, such as field programmable gate arrays, manage the required functions. PLD based systems provide higher levels of performance compared with microprocessor based systems because PLD systems can process the data in parallel while microprocessor based systems process the data sequentially. In this research, a bistable trip logic in a reactor protection system (RPS) was developed using very high speed integrated circuits hardware description language (VHDL), which is a hardware description language used in electronic design to describe the behavior of the digital system. Functional verifications were also performed in order to verify that the bistable trip logic was designed correctly and satisfied the required specifications. For the functional verification, a random testing technique was adopted to generate test inputs for the bistable trip logic.

• 한국전자파학회논문지
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• 제27권10호
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• pp.917-925
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• 2016

슈미트 트리거 로직(Schmitt Trigger Logic)은 디지털 회로의 노이즈에 대한 내성을 향상시키기 위해 히스테리시스 특성을 보이는 게이트를 제안한 설계 방법이다. 슈미트 트리거 특성을 보이는 설계 방법 중 최근에 제안된 substrate bias를 조정하여 구현하는 Dynamic Threshold voltage MOS(DTMOS) 방법을 사용할 경우, 게이트 수를 늘이지 않고 내성을 향상 시킬 수 있는 설계방법이나, 범용 CMOS 공정에서 구현하여 시뮬레이션으로 예상하는 성능을 얻을 수 있는지는 검증되지 않았다. 본 연구에서는 $0.18{\mu}m$ CMOS 공정에서 DTMOS 설계 방법을 구현하여 히스테리시스 특성을 측정하여 검증하였다. DTMOS 슈미트 트리거 버퍼, 인버터, 낸드, 노어 게이트 및 간단한 디지털 로직 회로를 제작하였으며, 히스테리시스 특성, 전력 소모, 딜레이 등의 특성들을 관찰하고, 일반적인 CMOS 게이트로 구현된 회로와 비교하였다. 노이즈에 대한 내성이 향상되는 것을 Direct Power Injection(DPI) 실험을 통해 확인하였다. 본 논문을 통해 제작된 DTMOS 슈미트 트리거 로직은 10 M~1 GHz 영역에서 전자파 내성이 향상된 것을 확인할 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권6호
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• pp.664-670
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• 2015

A four-times-VDD switch that supports high and low voltage mode operations is demonstrated in a generic 65 nm logic process. The proposed switch shows the robust operation for supply voltages ranging from VDD to $4{\times}VDD$. A cascaded voltage switch and a voltage doubler based charge pump generate the intermediate supply voltage levels required for the proposed high voltage switch. All the high voltage circuits developed in this work can be implemented using standard logic transistors without being subject to any voltage overstress.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부 B
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• pp.493-495
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• 1998

Robust design is one method to make manufacturing less sensitive to manufacturing process. Also it is cost effective technique to improve the quality process. This method uses statistically planned experiments to vary settings of important process control parameters. In this paper we apply fuzzy optimization and fuzzy logic system to robust design concept. First a method which uses fuzzy optimization in obtaining optimum settings by measured data from experiments will be presented. Second, fuzzy logic system is made to reduce experiments using experiments results consisted with key control parameter combinations. Then optimum parameter set points are obtained by the descrebed first fuzzy optimization method after prediction the results of each parameter combinations considering each control parameter variations by nonsingleton fuzzy logic system concept.

• 산업경영시스템학회지
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• 제31권3호
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• pp.80-89
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• 2008

Because of different hardware specifications, there are no unified protocol commands to use with various kinds of RFID readers. The current commercial RFID middlewares do not satisfy the various requirements from users to support business process logic representation. The EPCglobal, which is leading organization for the RFID research, suggested a RFID middleware architecture which is called ALE(Application Level Events) standard. However, their architecture also does not provide the application level's interfaces. Therefore, a new RFID middleware architecture is required to provide basic RFID functions, conform to ALE's specification and, additionally, support application level's business logic representation. This paper proposes a ALE-based RFID middleware architecture which provides business process logic representation. At first, the basic RFID control functionalities are identified. Secondly, the business process logic requirements in RFID applications are identified and classified Into six categories. Third, the Middelware architecture is implemented with Java and XML technology so that it can easily extended to support the various RFID hardware's protocols. Finally, an example RFID prototype system is developed to show the proposed architecture's feasibility and validate it. The proposed middleware is expected to be used In various application areas since it is using XML technology for easy adaptation and it also con- forms to ALE interface which is standard specification.

• Journal of the Optical Society of Korea
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• 제9권3호
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• pp.111-118
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• 2005

In this paper, a new optical parallel binary arithmetic processor (OPBAP) capable of computing arbitrary n-bit look-ahead carry full-addition is proposed and implemented. The conventional Boolean algebra is considered to implement OPBAP by using two schemes of optical logic processor. One is space-variant optical logic gate processor (SVOLGP), the other is shadow-casting optical logic array processor (SCOLAP). SVOLGP can process logical AND and OR operations different in space simultaneously by using free-space interconnection logic filters, while SCOLAP can perform any possible 16 Boolean logic function by using spatial instruction-control filter. A dual-rail encoding method is adopted because the complement of an input is needed in arithmetic process. Experiment on OPBAP for an 8-bit look-ahead carry full addition is performed. The experimental results have shown that the proposed OPBAP has a capability of optical look-ahead carry full-addition with high computing speed regardless of the data length.

• ETRI Journal
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• 제41권3호
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• pp.383-395
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• 2019

Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high-speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high-speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan-in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 2001년도 추계학술대회 학술발표 논문집
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• pp.65-68
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• 2001

Short shot is a molded part that is incomplete since insufficient material was injected into the mold. Remedial actions to solve short shot can be done by injection molding experts based on their empirical knowledge. Modifying mold and part, changing resin to less viscous one, and adjusting process conditions are general remedies. Experts of injection molding might try to adjust process conditions such as mold temperature, melt temperature, injection time based on their empirical knowledge as the first remedy because adjustment of process conditions is the most economic way in time and cost. However it is difficult to find appropriate process conditions as they are highly coupled and there are so many elements to be considered. In this paper, a fuzzy logic algorithm has been proposed to find an appropriate mold temperature. With the percentage of the insufficient Quantity of an injection molded part, an appropriate mold temperature can be obtained by the fuzzy logic algorithm.